34LC02-I/MS Microchip Technology, 34LC02-I/MS Datasheet - Page 10
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34LC02-I/MS
Manufacturer Part Number
34LC02-I/MS
Description
IC EEPROM 2KBIT 1MHZ 8MSOP
Manufacturer
Microchip Technology
Specifications of 34LC02-I/MS
Memory Size
2K (256 x 8)
Package / Case
8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Speed
1MHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.2 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Organization
256 K x 8
Interface Type
I2C
Maximum Clock Frequency
1 MHz
Access Time
400 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.2 V
Maximum Operating Current
3 mA
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
2.5 V, 3.3 V, 5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
34AA02/34LC02
6.0
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to ‘
of read operations: current address read, random read
and sequential read.
6.1
The 34XX02 contains an address counter that
maintains the address of the last word accessed, inter-
nally incremented by ‘
access (either a read or write operation) was to
address
would access data from address
the slave address with R/W bit set to ‘
issues an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer, but
does generate a Stop condition and the 34XX02
discontinues transmission (Figure 6-1).
6.2
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is done by sending the word address to the
34XX02 as part of a write operation. Once the word
address is sent, the master generates a Start condition
following the acknowledge. This terminates the write
operation, but not before the internal Address Pointer is
set. The master then issues the control byte again, but
with the R/W bit set to a ‘
an acknowledge and transmits the 8-bit data word. The
master will not acknowledge the transfer, but does
generate
discontinues transmission (Figure 6-2).
FIGURE 6-1:
DS22029D-page 10
READ OPERATION
Current Address Read
Random Read
n
, the next current address read operation
a
Stop
Bus Activity
Master
SDA Line
Bus Activity
condition
CURRENT ADDRESS READ
1
1
’. There are three basic types
’. Therefore, if the previous
1
’. The 34XX02 then issues
n+1
and
S
T
A
R
T
S
. Upon receipt of
1
’, the 34XX02
the
34XX02
Control
Byte
6.3
Sequential reads are initiated in the same way as a
random read, with the exception that after the 34XX02
transmits the first data byte, the master issues acknowl-
edge, as opposed to a Stop condition in a random read.
This directs the 34XX02 to transmit the next sequen-
tially addressed 8-bit word (Figure 6-3).
To provide sequential reads, the 34XX02 contains an
internal Address Pointer, which is incremented by one
at the completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.
6.4
The Chip Select bits (A2, A1, A0) can be used to
expand the contiguous address space for up to 16K bits
by adding up to eight 34XX02 devices on the same
bus. In this case, software can use A0 of the control
byte as address bit A8; A1 as address bit A9, and A2
as address bit A10. It is not possible to sequentially
read across device boundaries.
6.5
The 34XX02 employs a V
which disables the internal erase/write logic if the V
is below 1.35V at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.
A
C
K
Sequential Read
Contiguous Addressing Across
Multiple Devices
Noise Protection and Brown-Out
Data (n)
© 2008 Microchip Technology Inc.
CC
threshold detector circuit
N
O
C
A
K
P
S
T
O
P
CC