74VHC74MTC_Q Fairchild Semiconductor, 74VHC74MTC_Q Datasheet - Page 9

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74VHC74MTC_Q

Manufacturer Part Number
74VHC74MTC_Q
Description
Flip Flops Dl D-Type Flip-Flop
Manufacturer
Fairchild Semiconductor
Datasheet

Specifications of 74VHC74MTC_Q

Number Of Circuits
2
Logic Family
74VHC
Logic Type
D-Type Flip-Flop
Polarity
Inverting/Non-Inverting
Input Type
Single-Ended
Output Type
Differential
Propagation Delay Time
15.4 ns
High Level Output Current
- 8 mA
Low Level Output Current
8 mA
Supply Voltage - Max
5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
TSSOP-14
Minimum Operating Temperature
- 40 C
Number Of Input Lines
1
Number Of Output Lines
1
Supply Voltage - Min
2 V
©1992 Fairchild Semiconductor Corporation
74VHC74 Rev. 1.3.0
Physical Dimensions
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
(1.74)
3.17
3.81
NOTES: UNLESS OTHERWISE SPECIFIED
3.56
3.30
C)
A)
B) ALL DIMENSIONS ARE IN MILLIMETERS.
D) DIMENSIONS AND TOLERANCES PER
E) DRAWING FILE NAME: MKT-N14AREV7
THIS PACKAGE CONFORMS TO
MOLD FLASH, AND TIE BAR EXTRUSIONS.
JEDEC MS-001 VARIATION BA
DIMENSIONS ARE EXCLUSIVE OF BURRS,
ASME Y14.5-1994
Figure 4. 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
14
1
0.58
0.35
(Continued)
19.56
18.80
1.77
1.14
2.54
8
7
0.38 MIN
9
5.33 MAX
6.60
6.09
8.12
7.62
8.82
www.fairchildsemi.com
0.35
0.20

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