74ACT377MTC_Q Fairchild Semiconductor, 74ACT377MTC_Q Datasheet

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74ACT377MTC_Q

Manufacturer Part Number
74ACT377MTC_Q
Description
Flip Flops Oct D Type Flip-Flop
Manufacturer
Fairchild Semiconductor
Datasheet

Specifications of 74ACT377MTC_Q

Number Of Circuits
8
Logic Family
74ACT
Logic Type
D-Type Flip-Flop
Polarity
Non-Inverting
Input Type
Single-Ended
Output Type
Single-Ended
Propagation Delay Time
10 ns
High Level Output Current
- 24 mA
Low Level Output Current
24 mA
Supply Voltage - Max
5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
TSSOP-20
Minimum Operating Temperature
- 40 C
Number Of Input Lines
8
Number Of Output Lines
3
Supply Voltage - Min
4.5 V
©1988 Fairchild Semiconductor Corporation
74AC377, 74ACT377 Rev. 1.6.1
74AC377, 74ACT377
Octal D-Type Flip-Flop with Clock Enable
Features
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
FACT™ is a trademark of Fairchild Semiconductor Corporation
74AC377SC
74AC377SJ
74AC377MTC
74ACT377SC
74ACT377SJ
74ACT377MTC
74ACT377PC
I
Ideal for addressable register applications
Clock enable for address and data synchronization
applications
Eight edge-triggered D-type flip-flops
Buffered common clock
Outputs source/sink 24mA
See 273 for master reset version
See 373 for transparent latch version
See 374 for 3-STATE version
ACT377 has TTL-compatible inputs
CC
Order Number
All packages are lead free per JEDEC: J-STD-020B standard.
reduced by 50%
Package
Number
MTC20
MTC20
M20D
M20D
M20B
M20B
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
.
General Description
The AC/ACT377 has eight edge-triggered, D-type flip-
flops with individual D inputs and Q outputs. The com-
mon buffered Clock (CP) input loads all flip-flops simulta-
neously, when the Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock
transition, is transferred to the corresponding flip-flop's Q
output. The CE input must be stable only one setup time
prior to the LOW-to-HIGH clock transition for predictable
operation.
Package Description
January 2008
www.fairchildsemi.com

Related parts for 74ACT377MTC_Q

74ACT377MTC_Q Summary of contents

Page 1

... N20A Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. FACT™ trademark of Fairchild Semiconductor Corporation ©1988 Fairchild Semiconductor Corporation 74AC377, 74ACT377 Rev. 1.6.1 General Description The AC/ACT377 has eight edge-triggered, D-type flip- flops with individual D inputs and Q outputs ...

Page 2

... Mode Select-Function Table Operating Mode Load ‘1' Load ‘0' Hold (Do Nothing) H HIGH Voltage Level L LOW Voltage Level X Immaterial LOW-to-HIGH Clock Transition ©1988 Fairchild Semiconductor Corporation 74AC377, 74ACT377 Rev. 1.6.1 Pin Descriptions Pin Names D –D Data Inputs Clock Enable (Active LOW) Q – ...

Page 3

... Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1988 Fairchild Semiconductor Corporation 74AC377, 74ACT377 Rev. 1.6.1 3 www.fairchildsemi.com ...

Page 4

... V Output Voltage O T Operating Temperature Minimum Input Edge Rate, AC Devices: V from 30 Minimum Input Edge Rate, ACT Devices: V from 0.8V to 2.0V ©1988 Fairchild Semiconductor Corporation 74AC377, 74ACT377 Rev. 1.6.1 Parameter Parameter , V @ 3.3V, 4.5V, 5. 4.5V, 5. Rating –0.5V to +7.0V –20mA +20mA –0. 0.5V CC – ...

Page 5

... All outputs loaded; thresholds on input associated with output under test. 2. Maximum test duration 2.0ms, one output loaded at a time and I @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5. ©1988 Fairchild Semiconductor Corporation 74AC377, 74ACT377 Rev. 1.6.1 T +25° ...

Page 6

... Output Current I OHD I Maximum CC Quiescent Supply Current Notes: 4. All outputs loaded; thresholds on input associated with output under test. 5. Maximum test duration 2.0ms, one output loaded at a time. ©1988 Fairchild Semiconductor Corporation 74AC377, 74ACT377 Rev. 1.6.1 T +25° (V) Conditions Typ. 4 ...

Page 7

... Setup Time, HIGH or LOW Hold Time, HIGH or LOW Pulse Width, W HIGH or LOW Note: 7. Voltage range 3.3 is 3.0V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V ©1988 Fairchild Semiconductor Corporation 74AC377, 74ACT377 Rev. 1.6.1 T +25°C A (6) V (V) Min. Typ. Max. CC 3.3 90 125 5 ...

Page 8

... Hold Time, HIGH or LOW Pulse Width, W HIGH or LOW Note: 9. Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Symbol Parameter C Input Capacitance IN C Power Dissipation Capacitance PD ©1988 Fairchild Semiconductor Corporation 74AC377, 74ACT377 Rev. 1.6.1 T +25° 50pF L (8) V (V) Min. Typ. Max. CC 5.0 140 175 5 ...

Page 9

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 10

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 11

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 12

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 13

... TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended exhaustive list of all such trademarks. ® ACEx Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ ...

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