72235LB15PF IDT, 72235LB15PF Datasheet - Page 8

• Manufacturer Part Number: 72235LB15PF
• Description: FIFO
• Manufacturer: IDT

Specifications of 72235LB15PF

• Part # Aliases: IDT72235LB15PF

write cycle, the Half-Full Flag goes LOW and will remain set until the difference
between the write pointer and read pointer is less than or equal to one half of
the total memory of the device. The Half-Full Flag (HF) is then reset to HIGH
by the LOW-to-HIGH transition of the Read Clock (RCLK). The HF is
asynchronous.
the previous device. This output acts as a signal to the next device in the Daisy
Chain by providing a pulse when the previous device writes to the last location
of memory.
NOTES:
1. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1.
2. The clocks (RCLK, WCLK) can be free-running during reset.
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
After half of the memory is filled, and at the LOW-to-HIGH transition of the next
In the Daisy Chain Depth Expansion mode, WXI is connected to WXO of
,
,
Q
0
,
- Q
,
,
17
t
t
t
RSF
RSF
RSF
t
RS
Figure 4. Reset Timing
t
RSS
8
READ EXPANSION OUT (RXO)
(RXI) is connected to Read Expansion Out (RXO) of the previous device. This
output acts as a signal to the next device in the Daisy Chain by providing a pulse
when the previous device reads from the last location of memory.
DATA OUTPUTS (Q0-Q17)
TM
In the Daisy Chain Depth Expansion configuration, Read Expansion In
Q
0
-Q
17
(2)
are data outputs for 18-bit wide data.
t
RSR
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
= 1
= 0
(1)
MARCH 2013
2766 drw 06