74ACTQ74SC_Q Fairchild Semiconductor, 74ACTQ74SC_Q Datasheet

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74ACTQ74SC_Q

Manufacturer Part Number
74ACTQ74SC_Q
Description
Flip Flops Dl D-Type Flip-Flop
Manufacturer
Fairchild Semiconductor
Datasheet

Specifications of 74ACTQ74SC_Q

Number Of Circuits
2
Logic Family
74ACT
Logic Type
D-Type Flip-Flop
Polarity
Inverting/Non-Inverting
Input Type
Single-Ended
Output Type
Differential
Propagation Delay Time
8 ns
High Level Output Current
- 24 mA
Low Level Output Current
24 mA
Supply Voltage - Max
5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SOIC-14
Minimum Operating Temperature
- 40 C
Number Of Input Lines
1
Number Of Output Lines
1
Supply Voltage - Min
4.5 V
©1993 Fairchild Semiconductor Corporation
74ACTQ74 Rev. 1.4
FACT™, FACT Quiet Series™, and GTO™ are trademarks of Fairchild Semiconductor Corporation.
74ACTQ74
Quiet Series Dual D-Type Positive Edge-Triggered Flip-Flop
Features
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagram
74ACTQ74SC
74ACTQ74SJ
I
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Guaranteed pin-to-pin skew AC performance
Improved latch-up immunity
4kV minimum ESD immunity
TTL-compatible inputs
CC
Number
Order
reduced by 50%
Package
Number
M14A
M14D
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
General Description
The 74ACTQ74 is a dual D-type flip-flop with Asynchro-
nous Clear and Set inputs and complementary (Q, Q)
outputs. Information at the input is transferred to the
outputs on the positive edge of the clock pulse. Clock
triggering occurs at a voltage level of the clock pulse and
is not directly related to the transition time of the positive-
going pulse. After the Clock Pulse input threshold volt-
age has been passed, the Data input is locked out and
information present will not be transferred to the outputs
until the next rising edge of the Clock Pulse input.
The ACTQ74 utilizes Fairchild Quiet Series technology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Series™ features
GTO™ output control and undershoot corrector in addi-
tion to a split ground bus for superior performance.
Asynchronous Inputs:
Pin Descriptions
D
CP
C
S
Q
D1
Package Description
1
D1
LOW input to S
LOW input to C
Clear and Set are independent of clock
Simultaneous LOW on C
Q HIGH
1
, D
, Q
1
, S
, C
, CP
2
1
Pin Names
D2
D2
, Q
2
2
, Q
2
D
D
(Set) sets Q to HIGH level
(Clear) sets Q to LOW level
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
D
Data Inputs
and S
Description
D
makes both Q and
www.fairchildsemi.com
May 2007
tm

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74ACTQ74SC_Q Summary of contents

Page 1

... M14D Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. Connection Diagram FACT™, FACT Quiet Series™, and GTO™ are trademarks of Fairchild Semiconductor Corporation. ©1993 Fairchild Semiconductor Corporation 74ACTQ74 Rev. 1.4 General Description ...

Page 2

... Logic Symbols IEEE/IEC Block Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1993 Fairchild Semiconductor Corporation 74ACTQ74 Rev. 1.4 Truth Table (Each Half) Inputs ...

Page 3

... Symbol V Supply Voltage CC V Input Voltage I V Output Voltage O T Operating Temperature A ∆ ∆ t Minimum Input Edge Rate: V from 0.8V to 2.0V ©1993 Fairchild Semiconductor Corporation 74ACTQ74 Rev. 1.4 Parameter Parameter @ 4.5V, 5. Rating –0.5V to +7.0V –20mA +20mA –0. 0.5V CC –20mA +20mA –0. 0.5V CC ± ...

Page 4

... Maximum test duration 2.0ms, one output loaded at a time. 3. Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND. 4. Max number of data inputs (n) switching. (n – 1) inputs switching 0V to 3V. Input-under-test switching threshold ( threshold (V ILD ©1993 Fairchild Semiconductor Corporation 74ACTQ74 Rev. 1.4 = +25° Conditions ...

Page 5

... Pulse Width t Recovery Time, REC Note: 7. Voltage range 5.0 is 5.0V ± 0.5V. Capacitance Symbol Parameter C Input Capacitance IN C Power Dissipation Capacitance PD ©1993 Fairchild Semiconductor Corporation 74ACTQ74 Rev. 1.4 = +25° 50pF C L (5) V (V) Min. Typ. Max. CC 5.0 145 200 5.0 3.0 7 5.0 3.0 6.5 (6) 5 ...

Page 6

... Figure 1. Quiet Output Noise Voltage Waveforms 5. Set the HFS generator input levels at 0V LOW and 3V HIGH for ACT devices and 0V LOW and 5V HIGH for AC devices. Verify levels with an oscilloscope. ©1993 Fairchild Semiconductor Corporation 74ACTQ74 Rev. 1 and ...

Page 7

... Physical Dimensions Dimensions are in inches (millimeters) unless otherwise noted. Figure 3. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow ©1993 Fairchild Semiconductor Corporation 74ACTQ74 Rev. 1.4 Package Number M14A 7 www.fairchildsemi.com ...

Page 8

... Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 4. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide ©1993 Fairchild Semiconductor Corporation 74ACTQ74 Rev. 1.4 Package Number M14D 8 www.fairchildsemi.com ...

Page 9

... TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended exhaustive list of all such trademarks. ® ACEx Across the board. Around the world.™ ActiveArray™ Bottomless™ Build it Now™ CoolFET™ ...

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