74VHC175M_Q Fairchild Semiconductor, 74VHC175M_Q Datasheet - Page 2

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74VHC175M_Q

Manufacturer Part Number
74VHC175M_Q
Description
Flip Flops Qd D-Type Flip-Flop
Manufacturer
Fairchild Semiconductor
Datasheet

Specifications of 74VHC175M_Q

Number Of Circuits
4
Logic Family
74VHC
Logic Type
D-Type Flip-Flop
Polarity
Inverting/Non-Inverting
Input Type
Single-Ended
Output Type
Differential
Propagation Delay Time
15 ns
High Level Output Current
- 8 mA
Low Level Output Current
8 mA
Supply Voltage - Max
5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SOIC-16
Minimum Operating Temperature
- 40 C
Number Of Input Lines
4
Number Of Output Lines
4
Supply Voltage - Min
2 V
©1993 Fairchild Semiconductor Corporation
74VHC175 Rev. 1.2
Logic Symbol
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
IEEE/IEC
2
Functional Description
The VHC175 consists of four edge-triggered D flip-flops
with individual D inputs and Q and Q outputs. The Clock
and Master Reset are common. The four flip-flops will
store the state of their individual D inputs on the LOW-to-
HIGH clock (CP) transition, causing individual Q and Q
outputs to follow. A LOW input on the Master Reset (MR)
will force all Q outputs LOW and Q outputs HIGH inde-
pendent of Clock or Data inputs. The VHC175 is useful
for general logic applications where a common Master
Reset and Clock are acceptable.
Truth Table
H = HIGH Voltage Level
L = LOW Voltage Level
t
t
n
n+1
= Bit Time before Clock Pulse
Inputs @ t
= Bit Time after Clock Pulse
MR = H
D
H
L
n
n
,
Q
H
L
Outputs @ t
n
www.fairchildsemi.com
n+1
Q
H
L
n

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