89H16NT16G2ZBHLG IDT, 89H16NT16G2ZBHLG Datasheet
89H16NT16G2ZBHLG
Specifications of 89H16NT16G2ZBHLG
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89H16NT16G2ZBHLG Summary of contents
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... Logically independent switches in the same device – Configurable downstream port device numbering – Supports dynamic reconfiguration of switch partitions IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 2013 Integrated Device Technology, Inc • Dynamic port reconfiguration — downstream, upstream, non-transparent bridge • ...
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Clocking – Supports 100 MHz and 125 MHz reference clock frequencies – Flexible port clocking modes • Common clock • Non-common clock • Local port clock with SSC (spread spectrum setting) and port reference clock input Hot-Plug and Hot ...
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Block Diagram Frame Buffer Transaction Layer Data Link Layer Multiplexer / Demultiplexer Phy Logical Layer SerDes (Port 0) Function Number NTB ports Mapping table for entire entries device Mapping windows Six 32-bits or three ...
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Each of the two SMBus interfaces contain an SMBus clock pin and an SMBus data pin. In addition, the slave SMBus has SSMBADDR1 and SSMBADDR2 pins. As shown in Figure 2, the master and slave SMBuses may only be used ...
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Signal Type PE00RN[0] I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pair for PE00RP[0] port 0. PE00TN[0] O PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit pair for PE00TP[0] port 0. PE01RN[0] I ...
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Signal Type PE14TN[0] O PCI Express Port 14 Serial Data Transmit. Differential PCI Express transmit pair for PE14TP[0] port 14. PE15RN[0] I PCI Express Port 15 Serial Data Receive. Differential PCI Express receive pair for PE15RP[0] port 15. PE15TN[0] O ...
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Signal Type MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus active and generating the clock only when the EEPROM or I/O Expanders are being accessed. MSMBDAT I/O Master SMBus ...
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Signal Type GPIO[4] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: FAILOVER0 1st Alternate function pin type: Input 1st Alternate function: When this signal changes state and the ...
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Signal Type CLKMODE[1:0] I Clock Mode. These signals determine the port clocking mode used by ports of the device. GCLKFSEL I Global Clock Frequency Select. These signals select the frequency of the GCLKP and GCLKN signals. 0x0 100 MHz 0x1 ...
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Signal Type REFRES[6:4,1,0] — External Reference Resistor. Reference for the corresponding SerDes bias currents and PLL calibration circuitry Ohm +/- 1% resistor should be connected from this pin to ground and isolated from any source of noise injection. ...
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Pin Characteristics Note: Some input pads of the switch do not contain internal pull-ups or pull-downs. Unused SMBus and System inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left ...
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Function Pin Name PCI Express Interface PE11TP[0] (cont.) PE12RN[0] PE12RP[0] PE12TN[0] PE12TP[0] PE13RN[0] PE13RP[0] PE13TN[0] PE13TP[0] PE14RN[0] PE14RP[0] PE14TN[0] PE14TP[0] PE15RN[0] PE15RP[0] PE15TN[0] PE15TP[0] PE16RN[0] PE16RP[0] PE16TN[0] PE16TP[0] PE17RN[0] PE17RP[0] PE17TN[0] PE17TP[0] PE18RN[0] PE18RP[0] PE18TN[0] PE18TP[0] PE19RN[0] PE19RP[0] PE19TN[0] PE19TP[0] ...
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Function Pin Name Reference Clocks GCLKN[1:0] GCLKP[1:0] P08CLKN P08CLKP P16CLKN P16CLKP SMBus MSMBCLK MSMBDAT SSMBADDR[2,1] SSMBCLK SSMBDAT General Purpose I/O GPIO[8:0] Stack Configuration STK2CFG[4:0] STK3CFG[4:0] System Pins CLKMODE[1:0] GCLKFSEL PERSTN RSTHALT SWMODE[3:0] EJTAG / JTAG JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N ...
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Logic Diagram — PES16NT16G2 Global Reference Clocks PCIe Switch SerDes Input Port 0 PCIe Switch SerDes Input Port 3 PCIe Switch SerDes Input Port 8 Note that in addition to P08CLKN/P, the only other local port reference clock is P16CLKN/P. ...
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... C-DC 1. The input clock frequency will be either 100 or 125 MHz depending on signal AC Timing Characteristics Parameter PCIe Transmit UI Unit Interval T Minimum Tx Eye Width TX-EYE T Maximum time between the jitter median and maxi- TX-EYE-MEDIAN-to- mum deviation from the median MAX-JITTER Rise/Fall Time: 20% - 80% ...
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... Minimum, Typical, and Maximum values meet the requirements under PCI Express Base Specification 2.1. Signal GPIO 1 GPIO[8:0] 1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. 2. The values for this symbol were determined by calculation, not by testing. EXTCLK GPIO (asynchronous input) ...
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Signal Symbol JTAG JTAG_TCK Tper_16a Thigh_16a, Tlow_16a 1 JTAG_TMS , Tsu_16b JTAG_TCK rising JTAG_TDI Thld_16b JTAG_TDO Tdo_16c JTAG_TCK falling 2 Tdz_16c 2 JTAG_TRST_N Tpw_16d Table 14 JTAG AC Timing Characteristics 1. The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should ...
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Recommended Operating Temperature Recommended Operating Supply Voltages — Commercial Temperature Symbol V CORE Internal logic supply DD V I/O I/O supply except for SerDes PEA PCI Express Analog Power PEHA PCI Express Analog High ...
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Power Consumption Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 16 (and also listed below). Maximum power is measured under the following conditions: 70°C Ambient, 85% ...
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Thermal Considerations This section describes thermal considerations for the PES16NT16G2 (19mm tion that is relevant to the thermal performance of the PES16NT16G2 switch. Symbol T J(max) T A(max) Effective Thermal Resistance, Junction-to-Ambient JA(effective) Thermal Resistance, Junction-to-Board JB ...
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DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 16. Note: See Table 10, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Description Serial Link PCIe Transmit V Differential peak-to-peak output ...
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I/O Type Parameter Description Serial Link PCIe Receive (cont.) V Differential input voltage (peak- RX-DIFFp-p to-peak) RL Receiver Differential Return RX-DIFF Loss RL Receiver Common Mode Return RX-CM Loss Z Differential input impedance RX-DIFF-DC (DC common mode impedance ...
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I/O Type Parameter Description Leakage Inputs I/O / LEAK W O Pull-ups/downs I/O LEAK WITH Pull-ups/downs 1. Minimum, Typical, and Maximum values meet the requirements under PCI Express Base Specification 2.1. Absolute Maximum Voltage Rating Core Supply 1.5V Warning: For ...
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Symbol Parameter DC Parameter for SCL Pin V Input Low IL (V) V Input High IH (V) I Input Low Leakage IL_Leak I Input High Leakage IH_Leak Table 22 SMBus DC Characterization Data (Part Data at ...
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Package Pinout — 324-BGA Signal Pinout for the PES16NT16G2 The following table lists the pin numbers and signal names for the PES16NT16G2 device. Note: Pins labeled NC are No Connection. Pin Function PE08TP0 A3 PE08TN0 A4 ...
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Pin Function Alt. Pin E7 V PEA F15 PEA F16 PETA F17 DD E10 V PETA F18 DD E11 V PEA G1 DD E12 V PEA G2 DD E13 V PEA G3 DD E14 ...
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Pin Function Alt. Pin J13 J14 V PETA L4 DD J15 J16 J17 PE01TN0 L7 J18 PE01TP0 L10 SS K3 PE13RN0 L11 K4 PE13RP0 ...
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Pin Function Alt. Pin R10 SS P3 PE15RN0 R11 P4 PE15RP0 R12 P5 SWMODE2 R13 P6 V PEA R14 PEA R15 PETA R16 PETA R17 ...
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Pin Function Alt. Pin V7 PE18TP0 V11 V8 PE19TP0 V12 V9 V V13 SS V10 V V14 SS Table 24 PES16NT16G2 324-Pin Signal Pin-Out (Part Function Alt. Pin P16CLKP V15 NC GCLKP1 V16 V17 ...
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PES16NT16G2 Package Drawing — 324-Pin HL/HLG324 April 16, 2013 ...
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PES16NT16G2 Package Drawing — Page Two April 16, 2013 ...
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Revision History October 27, 2010: Initial publication of final data sheet. November 11, 2010: Added ZB silicon on Ordering page. January 26, 2011: In Table 18, Power Consumption, revised IO (and Total) power numbers in Full Swing section and added ...
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... FCBGA package, Commercial Temp. 89H16NT16G2ZBHLG 324-ball Green FCBGA package, Commercial Temp. 89H16NT16G2ZCHLG 89H16NT16G2ZBHLI 324-ball FCBGA package, Industrial Temp. 89H16NT16G2ZBHLGI 324-ball Green FCBGA package, Industrial Temp. CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 ® DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’ ...