89H16NT16G2ZCHLG8 IDT, 89H16NT16G2ZCHLG8 Datasheet - Page 3

• Manufacturer Part Number: 89H16NT16G2ZCHLG8
• Description: Peripheral Drivers & Components - PCIs
• Manufacturer: IDT

Specifications of 89H16NT16G2ZCHLG8

• Rohs: yes
• Part # Aliases: IDT89H16NT16G2ZCHLG8

Block Diagram
SMBus Interface
allowing every configuration register in the device to be read or written by an external agent. The master interface allows the default configuration
register values of the PES16NT16G2 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface
is also used by an external Hot-Plug I/O expander.
The PES16NT16G2 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES16NT16G2,
NTB ports
Mapping table
entries
Mapping windows
Address translation Direct-address and
Doorbell registers
Message registers
Function
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
SerDes
(Port 0)
Logical
Layer
Phy
Up to 4
Up to 64 for entire
device
Six 32-bits or three
64-bits
lookup table trans-
lations
32 bits
4 inbound and out-
bound registers of
32-bits
Frame Buffer
Number
16-Port Switch Core / 16 Gen2 PCI Express Lanes
Multiplexer / Demultiplexer
Table 1 Non-Transparent Bridge Function Summary
Each device can be configured to have up to 4 NTB functions and can support up to 4 CPUs/roots.
Each device can have up to 64 masters ID for address and ID translations.
Each NT port has six BARs, where each BAR opening an NT window to another domain.
Lookup-table translation divides the BAR aperture into up to 24 segments, where each segment
has independent translation programming and is associated with an entry in a look-up table.
Doorbell register is used for event signaling between domains, where an outbound doorbell bit sets
a corresponding bit at the inbound doorbell in the other domain.
Message registers allow mailbox message passing between domains -- message placed in the
inbound register will be seen at the outbound register at the other domain.
Transaction Layer
Data Link Layer
Figure 1 PES16NT16G2 Block Diagram
SerDes
(Port 3)
Logical
Layer
Route Table
Phy
3 of 33
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
Arbitration
(Port 8)
Port
SerDes
Logical
Layer
Description
Phy
Scheduler
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
SerDes
Logical
(Port 19)
Layer
Phy
April 16, 2013