89HPES32T8ZHBXG IDT, 89HPES32T8ZHBXG Datasheet

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... PCI Express® Switch Flexible Architecture with Numerous Configuration Options – Automatic per port link width negotiation to x8, x4 – Automatic lane reversal on all ports – Automatic polarity inversion on all lanes – Ability to load device configuration from serial EEPROM Legacy Support – ...

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... I/O connectivity solution for applications requiring high throughput, low latency, and simple board layout with a minimum number of board layers. It provides connectivity for ports across 32 integrated serial lanes. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base specifica- tion revision 1.1. ...

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... Note: The configurations in the above diagram show the maximum port widths. The PES32T8 can negotiate to narrower port widths — x4, x2, or x1. SMBus Interface The PES32T8 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES32T8, allowing every configuration register in the device to be read or written by an external agent ...

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... IDT 89PES32T8 Data Sheet As shown in Figure 4, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure 4(a), the master and slave SMBuses are tied together and the PES32T8 acts both as a SMBus master as well as a SMBus slave on this bus. This requires that the SMBus master or processor that has access to PES32T8 registers supports SMBus arbitration ...

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... IDT 89PES32T8 Data Sheet Pin Description The following tables lists the functions of the pins provided on the PES32T8. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level ...

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... IDT 89PES32T8 Data Sheet Signal PE7TP[3:0] PE7TN[3:0] PEREFCLKP[2:1] PEREFCLKN[2:1] REFCLKM Signal MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT Type Name/Description O PCI Express Port 7 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 7. When port 6 is merged with port 7, these signals become port 6 transmit pairs for lanes 4 through 7 ...

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... IDT 89PES32T8 Data Sheet Signal GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] GPIO[8] GPIO[9] Type Name/Description I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 2 I/O General Purpose I/O ...

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... IDT 89PES32T8 Data Sheet Signal GPIO[10] GPIO[11] GPIO[12] GPIO[13] GPIO[14] GPIO[15] Signal CCLKDS CCLKUS MSMBSMODE P01MERGEN P23MERGEN Type Name/Description I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P5RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 5 I/O General Purpose I/O ...

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... IDT 89PES32T8 Data Sheet Signal P45MERGEN P67MERGEN PERSTN RSTHALT SWMODE[3:0] Signal JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N Type Name/Description I Port 4 and 5 Merge. P45MERGEN is an active low signal pulled low internally via a 251K ohm resistor. When this pin is low, port 4 is merged with port 5 to form a single x8 port. ...

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... IDT 89PES32T8 Data Sheet Signal V CORE APE Type Name/Description I Core VDD. Power supply for core logic. I I/O VDD. LVTTL I/O buffer power supply. I PCI Express Digital Power. PCI Express digital power used by the digital power of the SerDes. ...

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... IDT 89PES32T8 Data Sheet Pin Characteristics Note: Some input pads of the PES32T8 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption ...

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... IDT 89PES32T8 Data Sheet Function Pin Name PCI Express Inter- PEREFCLKN[2:1] face (cont.) PEREFCLKP[2:1] REFCLKM SMBus MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT General Purpose I/O GPIO[15:0] System Pins CCLKDS CCLKUS MSMBSMODE P01MERGEN P23MERGEN P45MERGEN P67MERGEN PERSTN RSTHALT SWMODE[3:0] EJTAG / JTAG JTAG_TCK JTAG_TDI ...

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... IDT 89PES32T8 Data Sheet Logic Diagram — PES32T8 Reference Clocks PCI Express Switch SerDes Input Port 0 PCI Express Switch SerDes Input Port 1 PCI Express Switch SerDes Input Port 2 PCI Express Switch SerDes Input Port 3 PCI Express Switch SerDes Input Port 4 PCI Express ...

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... TX-IDLE-TO-DIFF- DATA T Transmitter data skew between any 2 lanes TX-SKEW PCIe Receive UI Unit Interval T Minimum Receiver Eye Width (jitter tolerance) RX-EYE (with jitter) T Max time between jitter median & max deviation RX-EYE-MEDIUM TO MAX JITTER T Unexpected Idle Enter Detect Threshold Integration Time RX-IDLE-DET-DIFF- ...

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... Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1 Signal GPIO 1 GPIO[15:0] 1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. 2. The values for this symbol were determined by calculation, not by testing. GPIO (asynchronous input) Signal ...

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... IDT 89PES32T8 Data Sheet JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TDO JTAG_TRST_N Recommended Operating Supply Voltages Symbol V CORE Internal logic supply DD V I/O I/O supply except for SerDes LVPECL/CML PCI Express Digital Power DD V APE PCI Express Analog Power PCI Express Serial Data Transmit Termination ...

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... IDT 89PES32T8 Data Sheet Recommended Operating Temperature Power Consumption Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 13 (and also listed below). Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 13 (and also listed below) ...

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... A(allowed) J(desired 100 C - (5.0W * 7.6W/ A(allowed) An appropriate level of increased air flow and/or a heat sink can be added to achieve this lower ambient temperature. Please contact ssdhelp@idt.com for further assistance. Board Size Any θ is and assuming a system with 1m/S airflow, the actual value of T ...

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... IDT 89PES32T8 Data Sheet DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 13. Note: See Table 8, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Serial Link PCIe Transmit V Differential peak-to-peak output voltage TX-DIFFp-p V De-emphasized differential output voltage TX-DE-RATIO V DC Common mode voltage ...

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... IDT 89PES32T8 Data Sheet I/O Type Parameter Other I/Os LOW Drive I OL Output I OH High Drive I OL Output I OH Schmitt Trig ger Input V IH (STI) Input Capacitance C IN Leakage Inputs I/O / LEAK W O Pull-ups/downs I/O LEAK WITH Pull-ups/downs 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1. ...

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... IDT 89PES32T8 Data Sheet Package Pinout — 500-BGA Signal Pinout for PES32T8 The following table lists the pin numbers and signal names for the PES32T8 device. Pin Function Alt Pin CORE CORE ...

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... IDT 89PES32T8 Data Sheet Pin Function Alt Pin E17 E18 PE7RP01 H5 E19 V CORE H26 DD E20 PE7RP02 H27 E21 V H28 SS E22 PE7RP03 H29 E23 V H30 SS E24 V CORE J1 DD E25 GPIO_13 J2 E26 GPIO_10 1 J3 E27 GPIO_08 1 J4 E28 E29 V IO J26 ...

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... IDT 89PES32T8 Data Sheet Pin Function Alt Pin W5 PE2RP02 AC2 W26 PE5RP01 AC3 W27 PE5RN01 AC4 W28 V PE AC5 DD W29 PE5TP01 AC26 W30 PE5TN01 AC27 Y1 V AC28 APE AC29 AC30 AD1 CORE AD2 DD Y26 V CORE AD3 ...

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... IDT 89PES32T8 Data Sheet Pin Function Alt Pin AH23 V PE AJ10 DD AH24 V PE AJ11 TT AH25 SWMODE_1 AJ12 AH26 RSTHALT AJ13 AH27 GPIO_02 1 AJ14 AH28 V CORE AJ15 DD AH29 V AJ16 SS AH30 V CORE AJ17 DD AJ1 V AJ18 SS AJ2 V IO AJ19 DD AJ3 V AJ20 SS AJ4 MSMBCLK AJ21 ...

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... IDT 89PES32T8 Data Sheet Power Pins V Core V Core Y26 A4 AE1 A6 AE30 A29 AF2 B2 AF12 B4 AF16 B25 AF20 B29 AG2 C2 AG28 C4 AG30 C6 AH1 C28 AH28 D1 AH30 D28 AJ8 D30 AJ29 E2 AK2 E11 AK4 E15 AK6 E19 AK29 E24 F3 F27 F28 H5 M5 ...

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... IDT 89PES32T8 Data Sheet Ground Pins C17 A3 C21 A5 C23 A7 C25 A11 C29 A13 C30 A15 D3 A17 D5 A19 D7 A23 D9 A26 D11 A30 D13 B1 D15 B3 D17 B5 D19 B6 D21 B9 D23 B13 D27 B17 D29 B21 E1 B23 E7 B24 E9 B27 E13 B28 E17 B30 ...

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... IDT 89PES32T8 Data Sheet Signals Listed Alphabetically Signal Name CCLKDS CCLKUS GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06 GPIO_07 GPIO_08 GPIO_09 GPIO_10 GPIO_11 GPIO_12 GPIO_13 GPIO_14 GPIO_15 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N MSMBADDR_1 MSMBADDR_2 MSMBADDR_3 MSMBADDR_4 MSMBCLK MSMBDAT MSMBSMODE P01MERGEN P23MERGEN ...

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... IDT 89PES32T8 Data Sheet Signal Name PE0RN00 PE0RN01 PE0RN02 PE0RN03 PE0RP00 PE0RP01 PE0RP02 PE0RP03 PE0TN00 PE0TN01 PE0TN02 PE0TN03 PE0TP00 PE0TP01 PE0TP02 PE0TP03 PE1RN00 PE1RN01 PE1RN02 PE1RN03 PE1RP00 PE1RP01 PE1RP02 PE1RP03 PE1TN00 PE1TN01 PE1TN02 PE1TN03 PE1TP00 PE1TP01 PE1TP02 PE1TP03 PE2RN00 PE2RN01 PE2RN02 ...

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... IDT 89PES32T8 Data Sheet Signal Name PE2RP00 PE2RP01 PE2RP02 PE2RP03 PE2TN00 PE2TN01 PE2TN02 PE2TN03 PE2TP00 PE2TP01 PE2TP02 PE2TP03 PE3RN00 PE3RN01 PE3RN02 PE3RN03 PE3RP00 PE3RP01 PE3RP02 PE3RP03 PE3TN00 PE3TN01 PE3TN02 PE3TN03 PE3TP00 PE3TP01 PE3TP02 PE3TP03 PE4RN00 PE4RN01 PE4RN02 PE4RN03 PE4RP00 PE4RP01 PE4RP02 ...

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... IDT 89PES32T8 Data Sheet Signal Name PE4TN00 PE4TN01 PE4TN02 PE4TN03 PE4TP00 PE4TP01 PE4TP02 PE4TP03 PE5RN00 PE5RN01 PE5RN02 PE5RN03 PE5RP00 PE5RP01 PE5RP02 PE5RP03 PE5TN00 PE5TN01 PE5TN02 PE5TN03 PE5TP00 PE5TP01 PE5TP02 PE5TP03 PE6RN00 PE6RN01 PE6RN02 PE6RN03 PE6RP00 PE6RP01 PE6RP02 PE6RP03 PE6TN00 PE6TN01 PE6TN02 ...

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... IDT 89PES32T8 Data Sheet Signal Name PE6TP00 PE6TP01 PE6TP02 PE6TP03 PE7RN00 PE7RN01 PE7RN02 PE7RN03 PE7RP00 PE7RP01 PE7RP02 PE7RP03 PE7TN00 PE7TN01 PE7TN02 PE7TN03 PE7TP00 PE7TP01 PE7TP02 PE7TP03 PEREFCLKN1 PEREFCLKN2 PEREFCLKP1 PEREFCLKP2 PERSTN REFCLKM RSTHALT SSMBADDR_1 SSMBADDR_2 SSMBADDR_3 SSMBADDR_5 SSMBCLK SSMBDAT I/O Type Location ...

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... IDT 89PES32T8 Data Sheet Signal Name SWMODE_0 SWMODE_1 SWMODE_2 SWMODE_3 V CORE APE I/O Type Location I AJ25 I AH25 I AF25 I AG25 See Table 21 for a listing of power pins. IO, See Table 22 for a listing of ground pins. Table 23 89PES32T8 Alphabetical Signal List (Part ...

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... IDT 89PES32T8 Data Sheet PES32T8 Pinout — Top View Core (Power I/O (Power ...

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... IDT 89PES32T8 Data Sheet PES32T8 Package Drawing — 500-Pin BX500/BXG500 March 25, 2008 ...

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... IDT 89PES32T8 Data Sheet PES32T8 Package Drawing — Page Two March 25, 2008 ...

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... IDT 89PES32T8 Data Sheet Revision History February 8, 2007: Initial publication. April 4, 2007: In Table 3, revised description for MSMBCLK signal. May 30, 2007: Changed device revision in Ordering Information from ZD to ZH. November 14, 2007: Added new parameter, Termination Resistor, to Table 9, Input Clock Requirements. March 25, 2008: Added θ ...

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... A AAA NN Product Operating Device Family Voltage Family Valid Combinations 89HPES32T8ZHBX 500-ball BGA package, Commercial Temperature 89HPES32T8ZHBXG 500-ball Green BGA package, Commercial Temperature CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 ® NNAN AA AA Package Temp Range Product Device Detail ...