89HPES8NT2ZBBC IDT, 89HPES8NT2ZBBC Datasheet
89HPES8NT2ZBBC
Specifications of 89HPES8NT2ZBBC
Related parts for 89HPES8NT2ZBBC
89HPES8NT2ZBBC Summary of contents
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... PCIe® upstream port and an NTB down- stream port. The PES8NT2 is a part of the IDT PCIe System Intercon- nect Products and is intended to be used with IDT PCIe System Interconnect Switches. Together, the chipset targets multi-host and intel- ligent I/O applications such as communications, storage, and blade servers where inter-domain communication is required ...
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... During link training, link width is automatically negotiated. Each PES8NT2 port is capable of independently negotiating to a x4, x2 width. Thus, the PES8NT2 may be used in virtually any two port switch configuration (e.g., {x4, x4}, {x4, x2}, {x2, x2}, etc.). The PES8NT2 supports static lane reversal. For example, lane reversal for upstream ...
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... IDT 89HPES8NT2 Data Sheet Pin Description The following tables list the functions of the pins provided on the PES8NT2. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level ...
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... IDT 89HPES8NT2 Data Sheet Signal MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT Signal GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] Type Name/Description I Master SMBus Address. These pins determine the SMBus address of the serial EEPROM from which configuration information is loaded. I/O Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus ...
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... IDT 89HPES8NT2 Data Sheet Signal CCLKDS CCLKUS MSMBSMODE PENTBRSTN PERSTN RSTHALT SWMODE[3:0] Signal JTAG_TCK JTAG_TDI Type Name/Description I Common Clock Downstream. When the CCLKDS pin is asserted, it indi- cates that a common clock is being used between the downstream device and the downstream port. I Common Clock Upstream. When the CCLKUS pin is asserted, it indi- cates that a common clock is being used between the upstream device and the upstream port ...
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... IDT 89HPES8NT2 Data Sheet Signal JTAG_TDO JTAG_TMS JTAG_TRST_N Signal V CORE APE Type Name/Description O JTAG Data Output. This is the serial data shifted out from the boundary scan logic or JTAG Controller. When no data is being shifted out, this signal is tri-stated ...
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... IDT 89HPES8NT2 Data Sheet Pin Characteristics Note: Some input pads of the PES8NT2 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption ...
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... IDT 89HPES8NT2 Data Sheet Function JTAG Pin Name Type Buffer JTAG_TCK I LVTTL JTAG_TDI I JTAG_TDO O JTAG_TMS I JTAG_TRST_N I Table 7 Pin Characteristics (Part I/O Internal Notes Type Resistor STI pull-up pull-up Low Drive STI pull-up pull-up External pull-down January 5, 2009 ...
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... IDT 89HPES8NT2 Data Sheet Logic Diagram — PES8NT2 Reference Clocks PCI Express Switch SerDes Input Port A PCI Express Switch SerDes Input Port C Master SMBus Interface SSMBADDR[5,3:1] Slave SMBus Interface System Pins 2 PEREFCLKP 2 PEREFCLKN REFCLKM PEALREV PEARP[0] PEARN[0] PEARP[1] PEARN[1] PEARP[3] PEARN[3] ...
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... Maximum time to transition from valid idle to diff data TX-IDLE-TO-DIFF- DATA T Transmitter data skew between any 2 lanes TX-SKEW PCIe Receive UI Unit Interval T Minimum Receiver Eye Width (jitter tolerance) RX-EYE (with jitter) Description Min 4 Table 8 Input Clock Requirements Description Min 399.88 399.88 ...
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... Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1 Signal GPIO 1 GPIO[7:0] 1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. 2. The values for this symbol were determined by calculation, not by testing. Signal JTAG ...
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... IDT 89HPES8NT2 Data Sheet JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TDO JTAG_TRST_N Recommended Operating Supply Voltages Symbol Parameter V CORE Internal logic supply DD V I/O I/O supply except for SerDes LVPECL/CML PCI Express Digital Power DD V APE PCI Express Analog Power PCI Express Serial Data Transmit Termina- ...
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... IDT 89HPES8NT2 Data Sheet Recommended Operating Temperature Power Consumption Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 14. Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 14 ...
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... IDT 89HPES8NT2 Data Sheet DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 12. Note: See Table 7, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Serial Link PCIe Transmit V Differential peak-to-peak output voltage TX-DIFFp-p V De-emphasized differential output voltage TX-DE-RATIO V DC Common mode voltage ...
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... IDT 89HPES8NT2 Data Sheet I/O Type Parameter Other I/Os LOW Drive I OL Output I OH High Drive I OL Output I OH Schmitt Trig ger Input V IH (STI) Input Capacitance C IN Leakage Inputs I/O / LEAK W O Pull-ups/downs I/O LEAK WITH Pull-ups/downs 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.0a. ...
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... IDT 89HPES8NT2 Data Sheet Package Pinout — 324-BGA Signal Pinout for PES8NT2 The following table lists the pin numbers and signal names for the PES8NT2 device. Pin Function Alt Pin A1 V E10 E11 SS A3 PEARP03 E12 A4 V CORE E13 DD A5 ...
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... IDT 89HPES8NT2 Data Sheet Pin Function Alt Pin B17 V CORE G8 DD B18 V CORE G10 G11 G12 CORE G13 G14 G15 G16 G17 G18 SS C10 C11 C12 ...
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... IDT 89HPES8NT2 Data Sheet Pin Function Alt Pin D18 V CORE J10 E2 NC J11 E3 V CORE J12 J13 CORE J14 J15 J16 J17 J18 SS Alternate Signal Functions No Connection Pins Function Alt Pin V CORE ...
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... IDT 89HPES8NT2 Data Sheet Power Pins V Core V Core A10 F10 A12 F18 A14 G12 A15 B17 H10 B18 H12 C4 H18 C13 J6 C16 J9 D1 J10 D4 J13 D14 J15 D18 K18 E14 Core ...
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... IDT 89HPES8NT2 Data Sheet Ground Pins A17 A18 B10 B12 B14 B15 C11 D11 D13 D15 D16 G16 D17 H11 E11 H13 E13 H17 E16 ...
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... IDT 89HPES8NT2 Data Sheet Signals Listed Alphabetically Signal Name CCLKDS CCLKUS GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06 GPIO_07 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N MSMBADDR_1 MSMBADDR_2 MSMBADDR_3 MSMBADDR_4 MSMBCLK MSMBDAT MSMBSMODE No Connect I/O Type Location I/O U12 I/O V13 I/O U13 I/O T12 I/O R12 ...
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... IDT 89HPES8NT2 Data Sheet Signal Name PEALREV PEARN00 PEARN01 PEARN02 PEARN03 PEARP00 PEARP01 PEARP02 PEARP03 PEATN00 PEATN01 PEATN02 PEATN03 PEATP00 PEATP01 PEATP02 PEATP03 PECLREV PECRN00 PECRN01 PECRN02 PECRN03 PECRP00 PECRP01 PECRP02 PECRP03 PECTN00 PECTN01 PECTN02 PECTN03 PECTP00 PECTP01 PECTP02 PECTP03 PENTBRSTN ...
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... IDT 89HPES8NT2 Data Sheet Signal Name PEREFCLKN0 PEREFCLKN1 PEREFCLKP0 PEREFCLKP1 PERSTN REFCLKM RSTHALT SSMBADDR_1 SSMBADDR_2 SSMBADDR_3 SSMBADDR_5 SSMBCLK SSMBDAT SWMODE_0 SWMODE_1 SWMODE_2 SWMODE_3 V CORE APE I/O Type Location V16 V15 I T11 I T15 I R11 I V7 ...
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... IDT 89HPES8NT2 Data Sheet PES8NT2 Pinout — Top View Core (Power I/O (Power (Power (Power APE (Power ...
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... IDT 89HPES8NT2 Data Sheet PES8NT2 Package Drawing — 324-Pin BC324/BCG324 January 5, 2009 ...
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... IDT 89HPES8NT2 Data Sheet PES8NT2 Package Drawing — Page Two January 5, 2009 ...
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... IDT 89HPES8NT2 Data Sheet Revision History April 15, 2008: Initial publication of data sheet. January 5, 2009: On the Ordering Information page, changed silicon revision from January 5, 2009 ...
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... Ordering Information A AAA NN Product Operating Device Family Family Voltage Valid Combinations 89HPES8NT2ZBBC 324-pin BC324 package, Commercial Temperature 89HPES8NT2ZBBCG 324-pin Green BC324 package, Commercial Temperature CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 ® NNAAN AA AA Package Product Revision Detail ...