89H24NT24G2ZAHLI IDT, 89H24NT24G2ZAHLI Datasheet

89H24NT24G2ZAHLI

Manufacturer Part Number

89H24NT24G2ZAHLI

Description

Peripheral Drivers & Components - PCIs

Manufacturer

IDT

Datasheet

1.89H24NT24G2ZBHLG.pdf (35 pages)

Specifications of 89H24NT24G2ZAHLI

Part # Aliases

IDT89H24NT24G2ZAHLI

Current page: 1 of 35
Download datasheet (366Kb)

Device Overview

Express® switching solutions. The PES24NT24G2 is a 24-lane, 24-port

system interconnect switch optimized for PCI Express Gen2 packet

switching in high-performance applications, supporting multiple simulta-

neous peer-to-peer traffic flows. Target applications include multi-host or

intelligent I/O based systems where inter-domain communication is

required, such as servers, storage, communications, and embedded

systems.

Features

 2013 Integrated Device Technology, Inc

The 89HPES24NT24G2 is a member of the IDT family of PCI



– 24-lane, 24-port PCIe switch with flexible port configuration

– Integrated SerDes supports 5.0 GT/s Gen2 and 2.5 GT/s

– Delivers up to 24 GBps (192 Gbps) of switching capacity

– Supports 128 Bytes to 2 KB maximum payload size

– Low latency cut-through architecture

– Supports one virtual channel and eight traffic classes

– Twenty-four x1 ports configurable as follows:

– Automatic per port link width negotiation

– Crosslink support

– Automatic lane reversal

– Per lane SerDes configuration

– Supports up to 8 fully independent switch partitions

– Logically independent switches in the same device

– Configurable downstream port device numbering

– Supports dynamic reconfiguration of switch partitions

High Performance Non-Blocking Switch Architecture

Port Configurability

Innovative Switch Partitioning Feature

• One x8 stack

• Two x8 stacks configurable as:

• De-emphasis

• Receive equalization

• Drive strength

• Dynamic port reconfiguration — downstream, upstream,

• Dynamic migration of ports between partitions

Gen1 operation

(x8

non-transparent bridge

• Eight x1 ports (ports 0 through 7 are not capable of

• Two x8 ports

• Four x4 ports

• Eight x2 ports

• Sixteen x1 ports



merging with an adjacent port)



x1)

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.

24-Lane 24-Port PCIe® Gen2

System Interconnect Switch

1 of 35



– Supports up to 8 NT endpoints per switch, each endpoint can

– 6 BARs per NT Endpoint

– 32 inbound and outbound doorbell registers

– 4 inbound and outbound message registers

– Supports up to 64 masters

– Unlimited number of outstanding transactions

– Compliant with the PCI-SIG multicast

– Supports 64 multicast groups

– Supports multicast across non-transparent port

– Multicast overlay mechanism support

– ECRC regeneration support

– Supports up to 2 DMA upstream ports, each with 2 DMA chan-

– Supports 32-bit and 64-bit memory-to-memory transfers

– Supports DMA transfers to multicast groups

– Linked list descriptor-based operation

– Flexible addressing modes

– Port arbitration

– Request metering

– High performance switch core architecture

Non-Transparent Bridging (NTB) Support

Multicast

Integrated Direct Memory Access (DMA) Controllers

Quality of Service (QoS)

• Movable upstream port within and between switch partitions

• Bar address translation

• All BARs support 32/64-bit base and limit address translation

• Two BARs (BAR2 and BAR4) support look-up table based

• Fly-by translation provides reduced latency and increased

• Supports arbitrary source and destination address alignment

• Supports intra- as well as inter-partition data transfers using

• Linear addressing

• Constant addressing

• Round robin

• IDT proprietary feature that balances bandwidth among

• Combined Input Output Queued (CIOQ) switch architecture

communicate with other switch partitions or external PCIe

domains or CPUs

nels

address translation

performance over buffered approach

the non-transparent endpoint

switch ports for maximum system throughput

with large buffers

89HPES24NT24G2

Data Sheet

April 16, 2013

Related parts for 89H24NT24G2ZAHLI

89H24NT24G2ZAHLI Summary of contents

Page 1

... Dynamic port reconfiguration — downstream, upstream, non-transparent bridge • Dynamic migration of ports between partitions IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.  2013 Integrated Device Technology, Inc • Movable upstream port within and between switch partitions Non-Transparent Bridging (NTB) Support  ...

Page 2

Clocking – Supports 100 MHz and 125 MHz reference clock frequencies – Flexible port clocking modes • Common clock • Non-common clock • Local port clock with SSC (spread spectrum setting) and port reference clock input Hot-Plug and Hot ...

Page 3

Block Diagram Frame Buffer Transaction Layer Data Link Layer Multiplexer / Demultiplexer Phy Logical Layer SerDes x1 (Port 0) (Ports 0 through 7 are not capable of merging with an adjacent port) Function Number NTB ports Mapping ...

Page 4

SMBus Interface The PES24NT24G2 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES24NT24G2, allowing every configuration register in the device to be read or written by an external agent. The master interface ...

Page 5

Signal Type PE00RN[0] I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pair for PE00RP[0] port 0. PE00TN[0] O PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit pair for PE00TP[0] port 0. PE01RN[0] I ...

Page 6

Signal Type PE10TN[0] O PCI Express Port 10 Serial Data Transmit. Differential PCI Express transmit pair for PE10TP[0] port 10. PE11RN[0] I PCI Express Port 11 Serial Data Receive. Differential PCI Express receive pair for PE11RP[0] port 11. PE11TN[0] O ...

Page 7

Signal Type PE21TN[0] O PCI Express Port 21 Serial Data Transmit. Differential PCI Express transmit pair for PE21TP[0] port 21. PE22RN[0] I PCI Express Port 22 Serial Data Receive. Differential PCI Express receive pair for PE22RP[0] port 22. PE22TN[0] O ...

Page 8

Signal Type GPIO[0] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: PART0PERSTN 1st Alternate function pin type: Input/Output 1st Alternate function: Assertion of this signal initiated a partition ...

Page 9

Signal Type GPIO[6] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: FAILOVER1 1st Alternate function pin type: Input 1st Alternate function: When this signal changes state and the ...

Page 10

Signal Type PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside the device. RSTHALT I Reset Halt. When this signal is asserted during a switch fundamental reset sequence, the switch remains in a quasi-reset state with the ...

Page 11

Signal REFRES[7:0] REFRESPLL V CORE PEA DD V PEHA DD V PETA Pin Characteristics Note: Some input pads of the switch do not contain internal pull-ups or pull-downs. Unused SMBus and System ...

Page 12

Function Pin Name PCI Express Interface PE03RP[0] (cont.) PE03TN[0] PE03TP[0] PE04RN[0] PE04RP[0] PE04TN[0] PE04TP[0] PE05RN[0] PE05RP[0] PE05TN[0] PE05TP[0] PE06RN[0] PE06RP[0] PE06TN[0] PE06TP[0] PE07RN[0] PE07RP[0] PE07TN[0] PE07TP[0] PE08RN[0] PE08RP[0] PE08TN[0] PE08TP[0] PE09RN[0] PE09RP[0] PE09TN[0] PE09TP[0] PE10RN[0] PE10RP[0] PE10TN[0] PE10TP[0] PE11RN[0] PE11RP[0] ...

Page 13

Function Pin Name PCI Express Interface PE12TN[0] (cont.) PE12TP[0] PE13RN[0] PE13RP[0] PE13TN[0] PE13TP[0] PE14RN[0] PE14RP[0] PE14TN[0] PE14TP[0] PE15RN[0] PE15RP[0] PE15TN[0] PE15TP[0] PE16RN[0] PE16RP[0] PE16TN[0] PE16TP[0] PE17RN[0] PE17RP[0] PE17TN[0] PE17TP[0] PE18RN[0] PE18RP[0] PE18TN[0] PE18TP[0] PE19RN[0] PE19RP[0] PE19TN[0] PE19TP[0] PE20RN[0] PE20RP[0] PE20TN[0] ...

Page 14

Function Pin Name PCI Express Interface PE21TN[0] (cont.) PE21TP[0] PE22RN[0] PE22RP[0] PE22TN[0] PE22TP[0] PE23RN[0] PE23RP[0] PE23TN[0] PE23TP[0] Reference Clocks GCLKN[1:0] GCLKP[1:0] P08CLKN P08CLKP P16CLKN P16CLKP SMBus MSMBCLK MSMBDAT SSMBADDR[2,1] SSMBCLK SSMBDAT General Purpose I/O GPIO[8:0] Stack Configuration STK2CFG[4:0] STK3CFG[4:0] System ...

Page 15

Function Pin Name EJTAG / JTAG JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N SerDes Reference Resis- REFRES[7:0] tors REFRESPLL Table 10 Pin Characteristics (Part Internal resistor values under typical operating conditions are 92K  for pull-up and 91K ...

Page 16

Logic Diagram — PES24NT24G2 Global Reference Clocks PCIe Switch SerDes Input Port 0 PCIe Switch SerDes Input Port 7 PCIe Switch SerDes Input Port 8 Note that in addition to Port 8, Port 16 also has port clocks, P16CLKN/P. PCIe ...

Page 17

... C-DC 1. The input clock frequency will be either 100 or 125 MHz depending on signal AC Timing Characteristics Parameter PCIe Transmit UI Unit Interval T Minimum Tx Eye Width TX-EYE T Maximum time between the jitter median and maxi- TX-EYE-MEDIAN-to- mum deviation from the median MAX-JITTER Rise/Fall Time: 20% - 80% ...

Page 18

... Minimum, Typical, and Maximum values meet the requirements under PCI Express Base Specification 2.1. Signal GPIO 1 GPIO[8:0] 1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. 2. The values for this symbol were determined by calculation, not by testing. EXTCLK GPIO (asynchronous input) ...

Page 19

Signal Symbol JTAG JTAG_TCK Tper_16a Thigh_16a, Tlow_16a 1 JTAG_TMS , Tsu_16b JTAG_TCK rising JTAG_TDI Thld_16b JTAG_TDO Tdo_16c JTAG_TCK falling 2 Tdz_16c 2 JTAG_TRST_N Tpw_16d Table 14 JTAG AC Timing Characteristics 1. The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should ...

Page 20

Recommended Operating Temperature Recommended Operating Supply Voltages — Commercial Temperature Symbol V CORE Internal logic supply DD V I/O I/O supply except for SerDes PEA PCI Express Analog Power PEHA PCI Express Analog High ...

Page 21

Power Consumption Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 16 (and also listed below). Maximum power is measured under the following conditions: 70°C Ambient, 85% ...

Page 22

Note important for the reliability of this device in any user environment that the junction temperature not exceed the T specified in Table 19. Consequently, the effective junction to ambient thermal resistance ( maintained below the value determined ...

Page 23

DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 16. Note: See Table 10, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Description Serial Link PCIe Transmit V Differential peak-to-peak output ...

Page 24

I/O Type Parameter Description Serial Link PCIe Receive (cont.) V Differential input voltage (peak- RX-DIFFp-p to-peak) RL Receiver Differential Return RX-DIFF Loss RL Receiver Common Mode Return RX-CM Loss Z Differential input impedance RX-DIFF-DC (DC common mode impedance ...

Page 25

I/O Type Parameter Description Capacitance C IN Leakage Inputs I/O / LEAK W O Pull-ups/downs I/O LEAK WITH Pull-ups/downs 1. Minimum, Typical, and Maximum values meet the requirements under PCI Express Base Specification 2.1. Absolute Maximum Voltage Rating Core Supply ...

Page 26

Symbol Parameter DC Parameter for SCL Pin V Input Low IL (V) V Input High IH (V) I Input Low Leakage IL_Leak I Input High Leakage IH_Leak Table 22 SMBus DC Characterization Data (Part Data at ...

Page 27

Package Pinout — 324-BGA Signal Pinout for the PES24NT24G2 The following table lists the pin numbers and signal names for the PES24NT24G2 device. Note: Pins labeled NC are No Connection. Pin Function PE08TP0 A3 PE08TN0 A4 ...

Page 28

Pin Function Alt. Pin E7 V PEA F15 PEA F16 PETA F17 DD E10 V PETA F18 DD E11 V PEA G1 DD E12 V PEA G2 DD E13 V PEA G3 DD E14 ...

Page 29

Pin Function Alt. Pin J13 J14 V PETA L4 DD J15 J16 J17 PE01TN0 L7 J18 PE01TP0 L10 SS K3 PE13RN0 L11 K4 PE13RP0 ...

Page 30

Pin Function Alt. Pin R10 SS P3 PE15RN0 R11 P4 PE15RP0 R12 P5 SWMODE2 R13 P6 V PEA R14 PEA R15 PETA R16 PETA R17 ...

Page 31

Pin Function Alt. Pin V7 PE18TP0 V11 V8 PE19TP0 V12 V9 V V13 SS V10 V V14 SS Table 24 PES24NT24G2 324-Pin Signal Pin-Out (Part Function Alt. Pin P16CLKP V15 PE21TP0 GCLKP1 V16 V17 ...

Page 32

PES24NT24G2 Package Drawing — 324-Pin HL/HLG324 April 16, 2013 ...

Page 33

PES24NT24G2 Package Drawing — Page Two April 16, 2013 ...

Page 34

Revision History October 27, 2010: Initial publication of final data sheet. November 11, 2010: Added ZB silicon on Ordering page. January 26, 2011: In Table 18, Power Consumption, revised IO (and Total) power numbers in Full Swing section and added ...

Page 35

... IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. ...

Related keywords

89H24NT24G2ZAHLI datasheet
89H24NT24G2ZAHLI data sheet
89H24NT24G2ZAHLI pdf datasheet
89H24NT24G2ZAHLI component
89H24NT24G2ZAHLI part
89H24NT24G2ZAHLI distributor
89H24NT24G2ZAHLI RoHS
89H24NT24G2ZAHLI datasheet download