89H32NT8AG2ZCHLI IDT, 89H32NT8AG2ZCHLI Datasheet

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... Logically independent switches in the same device – Configurable downstream port device numbering – Supports dynamic reconfiguration of switch partitions IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.  2012 Integrated Device Technology, Inc 89HPES32NT24AG2 • Dynamic port reconfiguration — downstream, upstream, non-transparent bridge • ...

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... IDT 89HPES32NT24AG2 Data Sheet – High performance switch core architecture • Combined Input Output Queued (CIOQ) switch architecture with large buffers  Clocking – Supports 100 MHz and 125 MHz reference clock frequencies – Flexible port clocking modes • Common clock • ...

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... IDT 89HPES32NT24AG2 Data Sheet Block Diagram ...

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... IDT 89HPES32NT24AG2 Data Sheet SMBus Interface The PES32NT24AG2 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES32NT24AG2, allowing every configuration register in the device to be read or written by an external agent. The master interface allows the default configuration register values of the PES32NT24AG2 to be overridden following a reset with values programmed in an external serial EEPROM ...

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... IDT 89HPES32NT24AG2 Data Sheet Signal PE00RN[1:0] PE00RP[1:0] PE00TN[1:0] PE00TP[1:0] PE01RN[1:0] PE01RP[1:0] PE01TN[1:0] PE01TP[1:0] PE02RN[1:0] PE02RP[1:0] PE02TN[1:0] PE02TP[1:0] PE03RN[1:0] PE03RP[1:0] PE03TN[1:0] PE03TP[1:0] PE04RN[1:0] PE04RP[1:0] PE04TN[1:0] PE04TP[1:0] PE05RN[1:0] PE05RP[1:0] PE05TN[1:0] PE05TP[1:0] PE06RN[1:0] PE06RP[1:0] PE06TN[1:0] PE06TP[1:0] PE07RN[1:0] PE07RP[1:0] PE07TN[1:0] PE07TP[1:0] PE08RN[0] PE08RP[0] PE08TN[0] PE08TP[0] ...

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... IDT 89HPES32NT24AG2 Data Sheet Signal PE10TN[0] PE10TP[0] PE11RN[0] PE11RP[0] PE11TN[0] PE11TP[0] PE12RN[0] PE12RP[0] PE12TN[0] PE12TP[0] PE13RN[0] PE13RP[0] PE13TN[0] PE13TP[0] PE14RN[0] PE14RP[0] PE14TN[0] PE14TP[0] PE15RN[0] PE15RP[0] PE15TN[0] PE15TP[0] PE16RN[0] PE16RP[0] PE16TN[0] PE16TP[0] PE17RN[0] PE17RP[0] PE17TN[0] PE17TP[0] PE18RN[0] PE18RP[0] PE18TN[0] PE18TP[0] PE19RN[0] PE19RP[0] ...

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... IDT 89HPES32NT24AG2 Data Sheet Signal PE21TN[0] PE21TP[0] PE22RN[0] PE22RP[0] PE22TN[0] PE22TP[0] PE23RN[0] PE23RP[0] PE23TN[0] PE23TP[0] Signal GCLKN[1:0] GCLKP[1:0] P00CLKN P00CLKP P02CLKN P02CLKP P04CLKN P04CLKP P06CLKN P06CLKP P08CLKN P08CLKP P12CLKN P12CLKP P16CLKN P16CLKP P20CLKN P20CLKP Type Name/Description O PCI Express Port 21 Serial Data Transmit. Differential PCI Express transmit pair for port 21 ...

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... IDT 89HPES32NT24AG2 Data Sheet Signal MSMBCLK MSMBDAT SSMBADDR[2,1] SSMBCLK SSMBDAT Signal GPIO[0] GPIO[1] GPIO[2] GPIO[3] Type Name/Description I/O Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus active and generating the clock only when the EEPROM or I/O Expanders are being accessed. ...

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... IDT 89HPES32NT24AG2 Data Sheet Signal GPIO[4] GPIO[5] GPIO[6] GPIO[7] GPIO[8] Type Name/Description I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: FAILOVER0 1st Alternate function pin type: Input 1st Alternate function: When this signal changes state and the correspond- ing failover capability is enabled, a failover event is signaled ...

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... IDT 89HPES32NT24AG2 Data Sheet Signal STK0CFG[1:0] STK1CFG[1:0] STK2CFG[4:0] STK3CFG[4:0] Signal CLKMODE[1:0] GCLKFSEL PERSTN RSTHALT SWMODE[3:0] Type Name/Description I Stack 0 Configuration. These pins select the configuration of stack 0. I Stack 1 Configuration. These pins select the configuration of stack 1. I Stack 2 Configuration. These pins select the configuration of stack 2. ...

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... IDT 89HPES32NT24AG2 Data Sheet Signal JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N Signal REFRES[7:0] REFRESPLL V CORE PEA DD V PEHA DD V PETA Pin Characteristics Note: Some input pads of the switch do not contain internal pull-ups or pull-downs. Unused SMBus and System inputs should be tied off to appropriate levels ...

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... IDT 89HPES32NT24AG2 Data Sheet Function PCI Express Interface PE00RN[1:0] PE00RP[1:0] PE00TN[1:0] PE00TP[1:0] PE01RN[1:0] PE01RP[1:0] PE01TN[1:0] PE01TP[1:0] PE02RN[1:0] PE02RP[1:0] PE02TN[1:0] PE02TP[1:0] PE03RN[1:0] PE03RP[1:0] PE03TN[1:0] PE03TP[1:0] PE04RN[1:0] PE04RP[1:0] PE04TN[1:0] PE04TP[1:0] PE05RN[1:0] PE05RP[1:0] PE05TN[1:0] PE05TP[1:0] PE06RN[1:0] PE06RP[1:0] PE06TN[1:0] PE06TP[1:0] PE07RN[1:0] PE07RP[1:0] PE07TN[1:0] PE07TP[1:0] PE08RN[0] ...

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... IDT 89HPES32NT24AG2 Data Sheet Function PCI Express Interface PE08TP[0] (cont.) PE09RN[0] PE09RP[0] PE09TN[0] PE09TP[0] PE10RN[0] PE10RP[0] PE10TN[0] PE10TP[0] PE11RN[0] PE11RP[0] PE11TN[0] PE11TP[0] PE12RN[0] PE12RP[0] PE12TN[0] PE12TP[0] PE13RN[0] PE13RP[0] PE13TN[0] PE13TP[0] PE14RN[0] PE14RP[0] PE14TN[0] PE14TP[0] PE15RN[0] PE15RP[0] PE15TN[0] PE15TP[0] PE16RN[0] PE16RP[0] PE16TN[0] ...

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... IDT 89HPES32NT24AG2 Data Sheet Function PCI Express Interface PE18RN[0] (cont.) PE18RP[0] PE18TN[0] PE18TP[0] PE19RN[0] PE19RP[0] PE19TN[0] PE19TP[0] PE20RN[0] PE20RP[0] PE20TN[0] PE20TP[0] PE21RN[0] PE21RP[0] PE21TN[0] PE21TP[0] PE22RN[0] PE22RP[0] PE22TN[0] PE22TP[0] PE23RN[0] PE23RP[0] PE23TN[0] PE23TP[0] Pin Name Type Buffer I PCIe differential ...

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... IDT 89HPES32NT24AG2 Data Sheet Function Reference Clocks GCLKN[1:0] GCLKP[1:0] P00CLKN P00CLKP P02CLKN P02CLKP P04CLKN P04CLKP P06CLKN P06CLKP P08CLKN P08CLKP P12CLKN P12CLKP P16CLKN P16CLKP P20CLKN P20CLKP SMBus MSMBCLK MSMBDAT SSMBADDR[2,1] SSMBCLK SSMBDAT General Purpose I/O GPIO[8:0] Stack Configuration STK0CFG[1:0] STK1CFG[1:0] STK2CFG[4:0] STK3CFG[4:0] Pin Name ...

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... IDT 89HPES32NT24AG2 Data Sheet Function System Pins CLKMODE[1:0] GCLKFSEL PERSTN RSTHALT SWMODE[3:0] EJTAG / JTAG JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N SerDes Reference Resis- REFRES[7:0] tors REFRESPLL 1. Internal resistor values under typical operating conditions are 92K Ω for pull-up and 91K Ω for pull-down. ...

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... IDT 89HPES32NT24AG2 Data Sheet Logic Diagram — PES32NT24AG2 Global Reference Clocks PCIe Switch SerDes Input Port 0 PCIe Switch SerDes Input Port 1 PCIe Switch SerDes Input Port 7 PCIe Switch SerDes Input Port 8 Note that in addition to P00CLKN/P, the following ports have local port reference clocks: ...

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... Clock source output DC impedance C-DC 1. The input clock frequency will be either 100 or 125 MHz depending on signal AC Timing Characteristics Parameter PCIe Transmit UI Unit Interval T Minimum Tx Eye Width TX-EYE T Maximum time between the jitter median and maximum TX-EYE-MEDIAN-to- deviation from the median MAX-JITTER Rise/Fall Time: 20% - 80% ...

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... Minimum, Typical, and Maximum values meet the requirements under PCI Express Base Specification 2.1. Signal GPIO 1 GPIO[8:0] 1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. 2. The values for this symbol were determined by calculation, not by testing. EXTCLK GPIO (asynchronous input) ...

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... IDT 89HPES32NT24AG2 Data Sheet Signal Symbol JTAG JTAG_TCK Tper_16a Thigh_16a, Tlow_16a 1 JTAG_TMS , JTAG_TDI Thld_16b JTAG_TDO Tdz_16c JTAG_TRST_N Tpw_16d 1. The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high rising edge of JTAG_TCK when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state ...

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... IDT 89HPES32NT24AG2 Data Sheet Recommended Operating Temperature Recommended Operating Supply Voltages — Commercial Temperature Symbol V CORE Internal logic supply DD V I/O I/O supply except for SerDes PEA PCI Express Analog Power PEHA PCI Express Analog High Power PETA PCI Express Transmitter Analog Voltage ...

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... IDT 89HPES32NT24AG2 Data Sheet Power Consumption Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 16 (and also listed below). Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 16 (and also listed below) ...

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... IDT 89HPES32NT24AG2 Data Sheet Note important for the reliability of this device in any user environment that the junction temperature not exceed the T specified in Table 19. Consequently, the effective junction to ambient thermal resistance ( maintained below the value determined by the formula: θ )/P JA ...

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... IDT 89HPES32NT24AG2 Data Sheet DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 16. Note: See Table 10, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Description Serial Link PCIe Transmit V Differential peak-to-peak output TX-DIFFp-p voltage V Low-Drive Differential Peak to TX-DIFFp-p-LOW ...

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... IDT 89HPES32NT24AG2 Data Sheet I/O Type Parameter Description Serial Link PCIe Receive (cont.) V Differential input voltage (peak-to- RX-DIFFp-p peak) RL Receiver Differential Return Loss RX-DIFF RL Receiver Common Mode Return RX-CM Loss Z Differential input impedance (DC) RX-DIFF- common mode impedance RX--DC Z Powered down input common RX-COMM-DC ...

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... IDT 89HPES32NT24AG2 Data Sheet Absolute Maximum Voltage Rating Core Supply 1.5V Warning: For proper and reliable operation in adherence with this data sheet, the device should not exceed the recommended operating voltages in Table 16. The absolute maximum operating voltages in Table 21 are offered to provide guidelines for voltage excursions outside the recommended voltage ranges ...

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... IDT 89HPES32NT24AG2 Data Sheet Symbol F SCL T BUF T HD:STA T SU:STA T SU:STO T HD:DAT T SU:DAT T TIMEOUT T LOW T HIGH POR@10kHz 1. Data at room and hot temperature. SMBus @3.3V ±10% Parameter Min Clock frequency 5 Bus free time between Stop and 3.5 Start Start condition hold time 1 Start condition setup time ...

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... IDT 89HPES32NT24AG2 Data Sheet Package Pinout — 484-BGA Signal Pinout for the PES32NT24AG2 The following table lists the pin numbers and signal names for the PES32NT24AG2 device. Note: Pins labeled NC are No Connection. Pin Function A1 STK2CFG1 A2 STK2CFG2 A3 STK2CFG3 PE07TP1 A6 PE07TP0 ...

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... IDT 89HPES32NT24AG2 Data Sheet Pin Function D13 REFRES02 D14 PE05RN1 D15 PE05RN0 D16 V SS D17 PE04RN1 D18 PE04RN0 D19 V SS D20 JTAG_TDI D21 SSMBCLK D22 SSMBADDR2 P08CLKP PE07RP1 E8 PE07RP0 E10 PE06RP1 E11 ...

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... IDT 89HPES32NT24AG2 Data Sheet Pin Function PE09RN0 H5 PE09RP0 H6 V PETA PEHA CORE DD H10 V CORE DD H11 V SS H12 V SS H13 V CORE DD H14 V CORE DD H15 V SS H16 V PEHA DD H17 V PETA DD H18 PE03RP0 H19 PE03RN0 H20 V SS H21 ...

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... IDT 89HPES32NT24AG2 Data Sheet Pin Function L15 V SS L16 V PEA DD L17 V PEA DD L18 PE02RP0 L19 PE02RN0 L20 V SS L21 PE02TN0 L22 PE02TP0 PEA PEA CORE DD M10 V CORE DD M11 V CORE ...

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... IDT 89HPES32NT24AG2 Data Sheet Pin Function PETA PEHA CORE DD R10 V CORE DD R11 V SS R12 V SS R13 V CORE DD R14 V CORE DD R15 V SS R16 V PEHA DD R17 V PETA DD R18 V SS R19 V SS R20 V SS R21 V SS R22 V SS ...

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... IDT 89HPES32NT24AG2 Data Sheet Pin Function V17 PE23RP0 V18 V SS V19 V SS V20 P00CLKN V21 V SS V22 I I P12CLKN PE16RN0 W7 PE17RN0 PE18RN0 W10 PE19RN0 W11 V SS W12 V SS W13 PE20RN0 W14 PE21RN0 W15 ...

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... IDT 89HPES32NT24AG2 Data Sheet Pin Function AB7 V SS AB8 PE18TP0 AB9 PE19TP0 AB10 V SS AB11 P16CLKP AB12 P20CLKP Alt. Pin Function Alt. AB13 V SS AB14 PE20TP0 AB15 PE21TP0 AB16 V SS AB17 PE22TP0 AB18 PE23TP0 Table 24 PES32NT24AG2 Signal Pin-Out (Part ...

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... IDT 89HPES32NT24AG2 Data Sheet PES32NT24AG2 Package Drawing — 484-Pin HL/HLG484 18.8mm March 14, 2012 ...

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... IDT 89HPES32NT24AG2 Data Sheet PES32NT24AG2 Package Drawing — Page Two March 14, 2012 ...

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... IDT 89HPES32NT24AG2 Data Sheet Revision History October 27, 2010: Initial publication of final data sheet. November 11, 2010: Added ZB silicon on Ordering page. January 26, 2011: In Table 18, Power Consumption, revised IO (and Total) power numbers in Full Swing section and added Half Swing section. Adjusted P value in Table 19. ...

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... Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’ ...