89H32T8G2ZCBLI IDT, 89H32T8G2ZCBLI Datasheet
89H32T8G2ZCBLI
Specifications of 89H32T8G2ZCBLI
Related parts for 89H32T8G2ZCBLI
89H32T8G2ZCBLI Summary of contents
Page 1
... Autonomous and software managed link width and speed control – Per lane SerDes configuration • De-emphasis • Receive equalization IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 2011 Integrated Device Technology, Inc. 32-Lane 8-Port PCIe® Gen2 I/O Expansion Switch • Drive strength ...
Page 2
... It provides 32 GBps (256 Gbps) of aggregated, full-duplex switching capacity through 32 integrated serial lanes, using proven and robust IDT technology. Each lane provides 5 GT/s of band- width in both directions and is fully compliant with PCI Express Base Specification, Revision 2.0. The PES32T8G2 is based on a flexible and efficient layered archi- tecture ...
Page 3
... IDT 89HPES32T8G2 Data Sheet Block Diagram I Frame Buffer Transaction Layer Data Link Layer Multiplexer / Demultiplexer Phy Phy Phy Phy Logical Logical Logical Logical Layer Layer Layer Layer SerDes SerDes SerDes SerDes (Port 0) SMBus Interface The PES32T8G2 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES32T8G2, allowing every configuration register in the device to be read or written by an external agent ...
Page 4
... IDT 89HPES32T8G2 Data Sheet Hot-Plug Interface The PES32T8G2 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES32T8G2 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configura- tion, whenever the state of a Hot-Plug output needs to be modified, the PES32T8G2 generates an SMBus transaction to the I/O expander with the new value of all of the outputs ...
Page 5
... IDT 89HPES32T8G2 Data Sheet Pin Description The following tables list the functions of the pins provided on the PES32T8G2. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level ...
Page 6
... IDT 89HPES32T8G2 Data Sheet Signal GCLKN[1:0] GCLKP[1:0] Signal MSMBCLK MSMBDAT SSMBADDR[2,1] SSMBCLK SSMBDAT Signal GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] Type Name/Description I Global Reference Clock. Differential reference clock input pair. This clock is used as the reference clock by on-chip PLLs to generate the clocks required for the system logic ...
Page 7
... IDT 89HPES32T8G2 Data Sheet Signal GPIO[6] GPIO[7] GPIO[8] Signal CLKMODE[1:0] GCLKFSEL P01MERGEN P23MERGEN P45MERGEN P67MERGEN Type Name/Description I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. ...
Page 8
... IDT 89HPES32T8G2 Data Sheet Signal PERSTN RSTHALT SWMODE[3:0] Signal JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N Type Name/Description I Global Reset. Assertion of this signal resets all logic inside PES32T8G2. I Reset Halt. When this signal is asserted during a PCI Express fundamental reset, PES32T8G2 executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active ...
Page 9
... IDT 89HPES32T8G2 Data Sheet Signal REFRES00 REFRES01 REFRES02 REFRES03 REFRES04 REFRES05 REFRES06 REFRES07 REFRESPLL V CORE PEA DD V PEHA DD V PETA Type Name/Description I/O Port 0 External Reference Resistor. Provides a reference for the Port 0 SerDes bias currents and PLL calibration circuitry kOhm +/- 1% resis- tor should be connected from this pin to ground ...
Page 10
... IDT 89HPES32T8G2 Data Sheet Pin Characteristics Note: Some input pads of the switch do not contain internal pull-ups or pull-downs. Unused SMBus and System inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, floating pins can cause a slight increase in power consumption ...
Page 11
... IDT 89HPES32T8G2 Data Sheet Function SMBus MSMBCLK MSMBDAT SSMBADDR[2,1] SSMBCLK SSMBDAT General Purpose I/O GPIO[8:0] System Pins CLKMODE[1:0] GCLKFSEL P01MERGEN P23MERGEN P45MERGEN P67MERGEN PERSTN RSTHALT SWMODE[3:0] EJTAG / JTAG JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N SerDes Reference REFRES00 Resistors REFRES01 REFRES02 REFRES03 REFRES04 REFRES05 ...
Page 12
... IDT 89HPES32T8G2 Data Sheet Logic Diagram — PES32T8G2 Global Reference Clocks PCI Express Switch SerDes Input Port 0 PCI Express Switch SerDes Input Port 1 PCI Express Switch SerDes Input Port 2 PCI Express Switch SerDes Input Port 7 Master SMBus Interface Slave SMBus Interface ...
Page 13
... Clock source output DC impedance C-DC 1. The input clock frequency will be either 100 or 125 MHz depending on signal AC Timing Characteristics Parameter PCIe Transmit UI Unit Interval T Minimum Tx Eye Width TX-EYE T Maximum time between the jitter median and maximum TX-EYE-MEDIAN-to- deviation from the median MAX-JITTER Rise/Fall Time: 20% - 80% ...
Page 14
... Minimum, Typical, and Maximum values meet the requirements under PCI Specification 2.0 Signal GPIO 1 GPIO[8:0] 1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. 2. The values for this symbol were determined by calculation, not by testing. Description 1 Min 399 ...
Page 15
... IDT 89HPES32T8G2 Data Sheet Signal JTAG JTAG_TCK 1 JTAG_TMS , JTAG_TDI JTAG_TDO JTAG_TRST_N 1. The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high rising edge of JTAG_TCK when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state ...
Page 16
... IDT 89HPES32T8G2 Data Sheet Recommended Operating Supply Voltages Symbol V CORE Internal logic supply DD V I/O I/O supply except for SerDes PEA PCI Express Analog Power PEHA PCI Express Analog High Power PETA PCI Express Transmitter Analog Voltage DD V Common ground SS 1 ...
Page 17
... IDT 89HPES32T8G2 Data Sheet Power Consumption Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 13 (and also listed below). Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 13 (and also listed below) ...
Page 18
... IDT 89HPES32T8G2 Data Sheet Thermal Considerations This section describes thermal considerations for the PES32T8G2 (23mm that is relevant to the thermal performance of the PES32T8G2 switch. Symbol T J(max) T A(max) θ Effective Thermal Resistance, Junction-to-Ambient JA(effective) θ Thermal Resistance, Junction-to-Board JB θ Thermal Resistance, Junction-to-Case ...
Page 19
... IDT 89HPES32T8G2 Data Sheet DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 13. Note: See Table 8, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Description Serial Link PCIe Transmit V Differential peak-to-peak output TX-DIFFp-p voltage V Low-Drive Differential Peak to TX-DIFFp-p-LOW ...
Page 20
... IDT 89HPES32T8G2 Data Sheet I/O Type Parameter Description Serial Link PCIe Receive (cont.) V Differential input voltage (peak-to- RX-DIFFp-p peak) RL Receiver Differential Return Loss RX-DIFF RL Receiver Common Mode Return RX-CM Loss Z Differential input impedance (DC) RX-DIFF- common mode impedance RX--DC Z Powered down input common RX-COMM-DC ...
Page 21
... IDT 89HPES32T8G2 Data Sheet Absolute Maximum Voltage Rating Core Supply 1.5V Warning: For proper and reliable operation in adherence with this data sheet, the device should not exceed the recommended operating voltages in Table 13. The absolute maximum operating voltages in Table 19 are offered to provide guidelines for voltage excursions outside the recommended voltage ranges ...
Page 22
... IDT 89HPES32T8G2 Data Sheet Symbol F SCL T BUF T HD:STA T SU:STA T SU:STO T HD:DAT T SU:DAT T TIMEOUT T LOW T HIGH POR@10kHz 1. Data at room and hot temperature. SMBus @3.3V ±10% Parameter Min Clock frequency 5 Bus free time between Stop and 3.5 Start Start condition hold time 1 Start condition setup time ...
Page 23
... IDT 89HPES32T8G2 Data Sheet Package Pinout — 484-BGA Signal Pinout The following table lists the pin numbers and signal names for the PES32T8G2 device. Pin Function Alt Pin A1 V B13 I/O B14 DD A3 PE03TP3 B15 A4 PE03TP2 B16 A5 V B17 SS A6 PE03TP1 ...
Page 24
... IDT 89HPES32T8G2 Data Sheet Pin Function Alt Pin G5 PE05RP2 H20 G6 V PEA H21 H22 CORE CORE J2 DD G10 G11 V CORE J4 DD G12 V CORE J5 DD G13 G14 V CORE J7 DD G15 V CORE J8 DD G16 G17 V PEA ...
Page 25
... IDT 89HPES32T8G2 Data Sheet Pin Function Alt Pin N21 V R14 SS N22 V R15 SS P1 PE04TP2 R16 P2 PE04TN2 R17 P3 V R18 R19 PETA R20 PETA R21 R22 CORE CORE T2 DD P10 P11 V CORE T4 DD P12 ...
Page 26
... IDT 89HPES32T8G2 Data Sheet Pin Function Alt Pin Y15 REFRES07 AA6 Y16 PE07RN2 AA7 Y17 V AA8 SS Y18 V AA9 SS Y19 PE07RN3 AA10 Y20 GPIO_06 AA11 Y21 GPIO_07 AA12 Y22 GPIO_08 1 AA13 AA1 CLKMODE0 AA14 AA2 GCLKFSEL AA15 AA3 SWMODE0 AA16 AA4 V AA17 ...
Page 27
... IDT 89HPES32T8G2 Data Sheet Power Pins V Core V Core K11 G9 K12 G11 K14 G12 K15 G14 L8 G15 L9 H8 L11 H9 L12 H11 L14 H12 L15 H14 M8 H15 M9 J8 M11 J9 M12 J11 M14 J12 M15 J14 N8 J15 N9 K8 N11 K9 N12 V Core PEA ...
Page 28
... IDT 89HPES32T8G2 Data Sheet Ground Pins A10 A13 A14 A15 B10 B13 B14 B15 C11 C12 C14 C17 L10 D4 H7 L13 D7 H10 L16 D9 H13 L20 D12 H16 M1 D14 H20 M2 D16 H21 ...
Page 29
... IDT 89HPES32T8G2 Data Sheet Signals Listed Alphabetically Signal Name CLKMODE0 CLKMODE1 GCLKFSEL GCLKN0 GCLKN1 GCLKP0 GCLKP1 GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06 GPIO_07 GPIO_08 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N MSMBCLK MSMBDAT NO CONNECTION P01MERGEN P23MERGEN P45MERGEN P67MERGEN I/O Type Location I AA1 I A21 ...
Page 30
... IDT 89HPES32T8G2 Data Sheet Signal Name PE00RN0 PE00RN1 PE00RN2 PE00RN3 PE00RP0 PE00RP1 PE00RP2 PE00RP3 PE00TN0 PE00TN1 PE00TN2 PE00TN3 PE00TP0 PE00TP1 PE00TP2 PE00TP3 PE01RN0 PE01RN1 PE01RN2 PE01RN3 PE01RP0 PE01RP1 PE01RP2 PE01RP3 PE01TN0 PE01TN1 PE01TN2 PE01TN3 PE01TP0 PE01TP1 PE01TP2 PE01TP3 PE02RN0 PE02RN1 PE02RN2 ...
Page 31
... IDT 89HPES32T8G2 Data Sheet Signal Name PE02RP0 PE02RP1 PE02RP2 PE02RP3 PE02TN0 PE02TN1 PE02TN2 PE02TN3 PE02TP0 PE02TP1 PE02TP2 PE02TP3 PE03RN0 PE03RN1 PE03RN2 PE03RN3 PE03RP0 PE03RP1 PE03RP2 PE03RP3 PE03TN0 PE03TN1 PE03TN2 PE03TN3 PE03TP0 PE03TP1 PE03TP2 PE03TP3 PE04RN0 PE04RN1 PE04RN2 PE04RN3 PE04RP0 PE04RP1 PE04RP2 ...
Page 32
... IDT 89HPES32T8G2 Data Sheet Signal Name PE04TN0 PE04TN1 PE04TN2 PE04TN3 PE04TP0 PE04TP1 PE04TP2 PE04TP3 PE05RN0 PE05RN1 PE05RN2 PE05RN3 PE05RP0 PE05RP1 PE05RP2 PE05RP3 PE05TN0 PE05TN1 PE05TN2 PE05TN3 PE05TP0 PE05TP1 PE05TP2 PE05TP3 PE06RN0 PE06RN1 PE06RN2 PE06RN3 PE06RP0 PE06RP1 PE06RP2 PE06RP3 PE06TN0 PE06TN1 PE06TN2 ...
Page 33
... IDT 89HPES32T8G2 Data Sheet Signal Name PE06TP0 PE06TP1 PE06TP2 PE06TP3 PE07RN0 PE07RN1 PE07RN2 PE07RN3 PE07RP0 PE07RP1 PE07RP2 PE07RP3 PE07TN0 PE07TN1 PE07TN2 PE07TN3 PE07TP0 PE07TP1 PE07TP2 PE07TP3 PERSTN REFRES00 REFRES01 REFRES02 REFRES03 REFRES04 REFRES05 REFRES06 REFRES07 REFRESPLL RSTHALT SSMBADDR1 SSMBADDR2 SSMBCLK SSMBDAT ...
Page 34
... IDT 89HPES32T8G2 Data Sheet Signal Name SWMODE0 SWMODE1 SWMODE2 SWMODE3 V CORE PEA I/O Type Location I AA3 I AB1 I AB3 I AB4 See Table 25 for a listing of power pins. DD- See Table 26 for a listing of ground pins. Table 27 PES32T8G2 Alphabetical Signal List (Part ...
Page 35
... IDT 89HPES32T8G2 Data Sheet PES32T8G2 Pinout — Top View Core (Power I/O (Power) DD Vss (Ground ...
Page 36
... IDT 89HPES32T8G2 Data Sheet PES32T8G2 Package Drawing — 484-Pin BL484/BR484 November 28, 2011 ...
Page 37
... IDT 89HPES32T8G2 Data Sheet PES32T8G2 Package Drawing — Page Two November 28, 2011 ...
Page 38
... IDT 89HPES32T8G2 Data Sheet Revision History January 21, 2010: Publication of Final data sheet. March 30, 2011: In Table 13, added V November 28, 2011: Added new Tables 20 and 21, SMBus Characterization and Timing. PETA to footnote # November 28, 2011 ...
Page 39
... Green FCBGA package, Industrial Temperature 89H32T8G2ZCBL 484-ball FCBGA package, Commercial Temperature 89H32T8G2ZCBLG 484-ball Green FCBGA package, Commercial Temperature 89H32T8G2ZCBLI 484-ball FCBGA package, Industrial Temperature 89H32T8G2ZCBLGI 484-ball Green FCBGA package, Industrial Temperature CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 ® ...