89H12NT12G2ZCHL IDT, 89H12NT12G2ZCHL Datasheet
89H12NT12G2ZCHL
Specifications of 89H12NT12G2ZCHL
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89H12NT12G2ZCHL Summary of contents
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... Dynamic port reconfiguration — downstream, upstream, non-transparent bridge • Dynamic migration of ports between partitions • Movable upstream port within and between switch partitions IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 2013 Integrated Device Technology, Inc Non-Transparent Bridging (NTB) Support ...
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Common clock • Non-common clock • Local port clock with SSC (spread spectrum setting) and port reference clock input Hot-Plug and Hot Swap – Hot-plug controller on all ports • Hot-plug supported on all downstream switch ports – ...
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Block Diagram Frame Buffer Transaction Layer Data Link Layer Multiplexer / Demultiplexer Phy Logical Layer SerDes x1 (Ports 0 through 3) Note: Ports 0 through 3 are not capable of merging with an adjacent port Function Number NTB ports Up ...
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SMBus Interface The PES12NT12G2 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES12NT12G2, allowing every configuration register in the device to be read or written by an external agent. The master interface ...
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Signal Type PE00RN[0] I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pair for PE00RP[0] port 0. PE00TN[0] O PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit pair for PE00TP[0] port 0. PE01RN[0] I ...
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Signal Type PE18TN[0] O PCI Express Port 18 Serial Data Transmit. Differential PCI Express transmit pair for PE18TP[0] port 18. PE19RN[0] I PCI Express Port 19 Serial Data Receive. Differential PCI Express receive pair for PE19RP[0] port 19. PE19TN[0] O ...
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Signal Type GPIO[0] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: PART0PERSTN 1st Alternate function pin type: Input/Output 1st Alternate function: Assertion of this signal initiated a partition ...
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Signal Type GPIO[6] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: FAILOVER1 1st Alternate function pin type: Input 1st Alternate function: When this signal changes state and the ...
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Signal Type PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside the device. RSTHALT I Reset Halt. When this signal is asserted during a switch fundamental reset sequence, the switch remains in a quasi-reset state with the ...
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Signal REFRES[6,4,1,0] REFRESPLL V CORE PEA DD V PEHA DD V PETA Pin Characteristics Note: Some input pads of the switch do not contain internal pull-ups or pull-downs. Unused SMBus and System ...
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Function Pin Name PCI Express Interface PE03RP[0] (cont.) PE03TN[0] PE03TP[0] PE08RN[0] PE08RP[0] PE08TN[0] PE08TP[0] PE09RN[0] PE09RP[0] PE09TN[0] PE09TP[0] PE10RN[0] PE10RP[0] PE10TN[0] PE10TP[0] PE11RN[0] PE11RP[0] PE11TN[0] PE11TP[0] PE16RN[0] PE16RP[0] PE16TN[0] PE16TP[0] PE17RN[0] PE17RP[0] PE17TN[0] PE17TP[0] PE18RN[0] PE18RP[0] PE18TN[0] PE18TP[0] PE19RN[0] PE19RP[0] ...
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Function Pin Name Reference Clocks GCLKN[1:0] GCLKP[1:0] P08CLKN P08CLKP P16CLKN P16CLKP SMBus MSMBCLK MSMBDAT SSMBADDR[2,1] SSMBCLK SSMBDAT General Purpose I/O GPIO[8:0] Stack Configuration STK2CFG[3:0] STK3CFG[4:0] System Pins CLKMODE[1:0] GCLKFSEL PERSTN RSTHALT SWMODE[3:0] EJTAG / JTAG JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N ...
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Logic Diagram — PES12NT12G2 Global Reference Clocks PCIe Switch SerDes Input Port 0 PCIe Switch SerDes Input Port 3 PCIe Switch SerDes Input Port 8 PCIe Switch SerDes Input Port 9 PCIe Switch SerDes Input Port 11 PCIe Switch SerDes ...
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... C-DC 1. The input clock frequency will be either 100 or 125 MHz depending on signal AC Timing Characteristics Parameter PCIe Transmit UI Unit Interval T Minimum Tx Eye Width TX-EYE T Maximum time between the jitter median and maxi- TX-EYE-MEDIAN-to- mum deviation from the median MAX-JITTER Rise/Fall Time: 20% - 80% ...
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... Minimum, Typical, and Maximum values meet the requirements under PCI Express Base Specification 2.1. Signal GPIO 1 GPIO[8:0] 1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. 2. The values for this symbol were determined by calculation, not by testing. EXTCLK GPIO (asynchronous input) ...
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Signal Symbol JTAG JTAG_TCK Tper_16a Thigh_16a, Tlow_16a 1 JTAG_TMS , Tsu_16b JTAG_TCK rising JTAG_TDI Thld_16b JTAG_TDO Tdo_16c JTAG_TCK falling 2 Tdz_16c 2 JTAG_TRST_N Tpw_16d Table 14 JTAG AC Timing Characteristics 1. The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should ...
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Recommended Operating Temperature Recommended Operating Supply Voltages — Commercial Temperature Symbol V CORE Internal logic supply DD V I/O I/O supply except for SerDes PEA PCI Express Analog Power PEHA PCI Express Analog High ...
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Power-Up/Power-Down Sequence During power supply ramp-up, V CORE must remain at least 1.0V below V DD ments for the various operating supply voltages. The power-down sequence can occur in any order. Power Consumption Typical power is measured under the following ...
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Symbol Parameter Effective Thermal Resistance, Junction-to-Ambient JA(effective) Thermal Resistance, Junction-to-Board JB Thermal Resistance, Junction-to-Case JC P Power Dissipation of the Device Table 19 Thermal Specifications for PES12NT12G2, 19x19 mm FCBGA324 Package Note important for the ...
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DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 16. Note: See Table 10, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Description Serial Link PCIe Transmit V Differential peak-to-peak output ...
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I/O Type Parameter Description Serial Link PCIe Receive (cont.) V Differential input voltage (peak- RX-DIFFp-p to-peak) RL Receiver Differential Return RX-DIFF Loss RL Receiver Common Mode Return RX-CM Loss Z Differential input impedance RX-DIFF-DC (DC common mode impedance ...
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I/O Type Parameter Description Capacitance C IN Leakage Inputs I/O / LEAK W O Pull-ups/downs I/O LEAK WITH Pull-ups/downs 1. Minimum, Typical, and Maximum values meet the requirements under PCI Express Base Specification 2.1. Absolute Maximum Voltage Rating Core Supply ...
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Symbol Parameter DC Parameter for SCL Pin V Input Low IL (V) V Input High IH (V) I Input Low Leakage IL_Leak I Input High Leakage IH_Leak Table 22 SMBus DC Characterization Data (Part Data at ...
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Package Pinout — 324-BGA Signal Pinout for the PES12NT12G2 The following table lists the pin numbers and signal names for the PES12NT12G2 device. Note: Pins labeled NC are No Connection. Pin Function PE08TP0 A3 PE08TN0 A4 ...
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Pin Function Alt. Pin E7 V PEA F15 PEA F16 PETA F17 DD E10 V PETA F18 DD E11 V PEA G1 DD E12 V PEA G2 DD E13 V PEA G3 DD E14 ...
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Pin Function Alt. Pin J13 J14 V PETA L4 DD J15 J16 J17 PE01TN0 L7 J18 PE01TP0 L10 L11 K4 NC ...
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Pin Function Alt. Pin R10 R11 P4 NC R12 P5 SWMODE2 R13 P6 V PEA R14 PEA R15 PETA R16 PETA R17 ...
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Pin Function Alt. Pin V7 PE18TP0 V11 V8 PE19TP0 V12 V9 V V13 SS V10 V V14 SS Table 24 PES12NT12G2 324-Pin Signal Pin-Out (Part Function Alt. Pin Function P16CLKP V15 NC GCLKP1 V16 ...
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PES12NT12G2 Package Drawing — 324-Pin HL/HLG324 April 16, 2013 ...
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PES12NT12G2 Package Drawing — Page Two April 16, 2013 ...
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Revision History October 27, 2010: Initial publication of final data sheet. November 11, 2010: Added ZB silicon on Ordering page. January 26, 2011: In Table 18, Power Consumption, revised IO (and Total) power numbers in Full Swing section and added ...
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... Voltage Detail Valid Combinations 89H12NT12G2ZBHL 324-ball FCBGA package, Commercial Temp. 89H12NT12G2ZBHLG 324-ball Green FCBGA package, Commercial Temp. 89H12NT12G2ZCHLG 89H12NT12G2ZBHLI 324-ball FCBGA package, Industrial Temp. 89H12NT12G2ZBHLGI 324-ball Green FCBGA package, Industrial Temp. CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 ® ...