TSI381-66IL IDT, TSI381-66IL Datasheet
TSI381-66IL
Manufacturer Part Number
TSI381-66IL
Description
Peripheral Drivers & Components - PCIs PCI-to-x1 PCIe Bridge
Manufacturer
IDT
Datasheet
1.TSI381-66IL.pdf
(2 pages)
Specifications of TSI381-66IL
Part # Aliases
IDTTSI381-66IL
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IDT, Integrated Device Technology Inc
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Features
General
PCI Express
PCI
Other Features
2008 Integrated Device Technology, Inc.
• PCI Express to PCI bridge
• Transparent, Non-transparent, and Opaque modes
• Efficient queuing and buffering for low latency and high
• Compliant with the following specifications:
• x1 lane PCIe Interface
• Advanced error reporting capability
• End-to-end CRC check and generation
• Up to four outstanding memory reads
• ASPM L0 link state power management
• Legacy interrupt signaling and MSI interrupts
• Hot Plug support
• 32/64-bit addressing and 32-bit data
• Operates at 25, 33, 50, and 66 MHz
• Up to eight outstanding memory reads
• 3.3V PCI I/Os, 5V tolerant
• Four external PCI masters supported through internal arbiter
• MSI generation and handling using interrupt and GPIO signals
• Masquerade mode
• JTAG IEEE 1149.1, 1149.6 to allow testing of the PCIe Interface
• Four GPIO pins and four interrupt pins that can generate MSIs
• D0, D3 hot, D3 cold power management state support
• 1.2V core power supply
• No power sequencing constraints
• Packaging:
throughput
– PCI Express Base 1.1
– PCI Express PCI/PCI-X Bridge 1.0
– PCI-to-PCI Bridge Architecture 1.2
– PCI Local Bus 3.0
– PCI Bus Power Management Interface 1.2
– 13x13 mm, 144-pin PBGA (10x10 mm option is available; part
– Pinout and footprint compatible with PLX PEX 8111/8112
– Industrial temperature operating range
– RoHS-compliant package available
number Tsi382)
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
®
Tsi381
Product Brief
1 of 2
™
Device Overview
PCI Express protocol to the PCI bus standard. The Tsi381’s PCIe Inter-
face supports a x1 lane PCIe configuration, which enables the bridge to
offer exceptional throughput performance of up to 2.5 Gbps per transmit
and receive direction.
offers designers extensive flexibility by supporting three types of
addressing modes: transparent, opaque, and non-transparent.
Simplest, Low-Risk Design
with no power sequencing constraints. Its package is designed to
simplify board layout for high reliability and signal integrity. A compre-
hensive suite of design support resources are also available to aid
designers.
for designers to migrate current designs to the Tsi381, and thereby bring
them to market quickly and with low risk.
The IDT Tsi381 is a high-performance bus bridge that connects the
The device’s PCI Interface can operate up to 66 MHz. This interface
Clocking/
Handling
The Tsi381 simplifies board design by using only two power supplies
Pin compatibility with the PLX PEX8111 and PEX8112 make it easy
Interrupt
Handling
PCIe
Arbiter
Reset
Error
GPIO
PCI
®
Posted
Writer
Posted
Buffer
Buffer
Non-
Downstream
Downstream
Mux Logic
to PCI Bridge
Figure 1 Block Diagram
Posted
Queue
Posted
Queue
Non-
PCIe Interface (x1)
PCI Interface
Posted
Posted
Writer
Buffer
Buffer
Non-
Upstream
Upstream
Mux Logic
Posted
Queue
Posted
Queue
Non-
August 14, 2009
80E2000_BK001_03 (Tsi381)
Controller
Registers
EEPROM
Config
Power
Mgmt
JTAG
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TSI381-66IL Summary of contents
Page 1
... Pin compatibility with the PLX PEX8111 and PEX8112 make it easy for designers to migrate current designs to the Tsi381, and thereby bring them to market quickly and with low risk PCI Bridge ...
Page 2
... Opaque mode provides semi-transparent operation for multi-processor configurations and enhanced private device support. Typical Applications The Tsi381 is suited to applications that need to bridge PCIe to downstream PCI devices. Its flexibility, high performance, small foot- print, and low power consumption, make it ideal for a wide range of applications, including: • ...