PEX8603-AA50NI-G PLX Technology, PEX8603-AA50NI-G Datasheet

PEX8603-AA50NI-G

Manufacturer Part Number

PEX8603-AA50NI-G

Description

Peripheral Drivers & Components - PCIs 3 lane 3 port Gen 2 PCIe Switch

Manufacturer

PLX Technology

Datasheet

1.PEX8603-AA50NI-G.pdf (3 pages)

Specifications of PEX8603-AA50NI-G

Rohs

yes

Mounting Style

SMD/SMT

Package / Case

QFN-136

Description/function

3 Lane, 3 Port PCIe Gen2 Switch

Number Of Drivers

Current page: 1 of 3
Download datasheet (256Kb)



Highlights

PEX8603 General Features

PEX8603 Key Features

o 3-lane, 3-port PCIe Gen2 switch

o 10 x 10mm

o Typical Power: 0.7 Watts

o Standards Compliant

o High Performance

o Flexible Configuration

o Quality of Service (QoS)

o Reliability, Availability,

o Power Management

 Integrate 5.0 GT/s SerDes

package

 PCI Express Base Specification, r2.1

 PCI Power Management Spec, r1.2

 Microsoft Windows 7 Compliant

 Dynamic SerDes speed control

 Non-blocking switch fabric

 Full line rate on all ports

 Packet Cut-Thru with 250ns max

 256B Max Payload Size

 Ports configurable as x1, x2

 Registers configurable with strapping

 Reference Clock Buffered Output

 Lane and polarity reversal

 Compatible with PCIe 1.0a PM

 Eight traffic classes per port

 Round-robin source port arbitration

 Relaxed PCI Ordering

Serviceability

 visionPAK™

 All ports hot plug capable thru I

 Data Path parity

 Memory (RAM) Error Correction

 INTA# and FATAL_ERR#

 Advanced Error Reporting

 Port Status bits and GPIO available

 Per port error diagnostics

 JTAG AC/DC boundary scan

 WAKE#, Beacon, Vaux support

(backwards compatible w/ PCIe

1.0a/1.1)

packet latency (x1 to x1)

pins, EEPROM, I

signals for downstream ports

• Per Port Performance Monitoring

• Per port payload & header counters

• SerDes Eye Capture

• Error Injection and Loopback

(Hot-Plug Controller on every port)

signals

, 136-pin QFN

C, or host software

The ExpressLane

enabling users to add scalable high bandwidth non-blocking interconnection

to a wide variety of applications including control plane applications,

consumer applications and embedded systems. The PEX8603 is well suited

for fan-out and peer-to-peer applications.

Low Packet Latency & High Performance

The PEX8603 architecture supports packet cut-thru with a maximum latency of

250ns in x1 to x1 configuration. This, combined with low power consumption

and non-blocking internal switch architecture, provides full line rate on all ports

for low-power applications such as consumer and embedded. The low latency

enables applications to achieve high throughput and performance. In addition to

low latency, the device supports a max payload size of 256 bytes.

Data Integrity

The PEX8603 provides end-to-end CRC protection (ECRC) and Poison bit

support to enable designs that require guaranteed error-free packets. PLX also

supports data path parity and memory (RAM) error correction as packets pass

through the switch.

Power Management and Reference Clock Buffers

The PEX8603 supports the following power management states: L0, L0s, L1,

L2/L3 Ready, L2 and L3. Moreover, the PEX8603 supports Vaux along with the

external signal WAKE# and the in-band Beacon for the PCIe endpoints to use to

inform the system host to exit the low power savings mode.

The PEX 8603 supports two pairs of buffered, 100 MHz HCSL output clocks,

one pair for each downstream port of the switch. Each clock output pair can be

disabled by software or serial EEPROM when not in use, for additional power

savings. This feature greatly reduces system BOM cost by eliminating the need

for extra clock buffers on the PCB.

Interoperability

The PEX8603 is designed to be fully compliant with the PCI Express Base

Specification r2.1 and is backwards compatible to PCI Express Base

Specification r1.1 and r1.0a. Additionally each port supports auto-negotiation and

polarity reversal. Furthermore, the PEX8603 is designed for Microsoft Windows

7 compliance. All PLX switches undergo thorough interoperability testing in

PLX’s Interoperability Lab and compliance testing at the PCI-SIG plug-fest to

ensure compatibility with PCI Express devices in the market.

Device Operation Configuration Flexibility

The PEX8603 provides several ways to configure its operations. The device can

be configured through strapping pins, I2C interface, CPU configuration cycles

and/or an optional serial EEPROM. This allows for easy debug during the

development phase and functional monitoring during the operation phase.

PEX8603, PCI Express Gen 2 Switch, 3 Lanes, 3 Ports

Page 1 of 3

™

PEX8603 device offers PCI Express switching capability

8/17/2011, Version 1.1

Related parts for PEX8603-AA50NI-G

PEX8603-AA50NI-G Summary of contents

Page 1

... Power Management and Reference Clock Buffers The PEX8603 supports the following power management states: L0, L0s, L1, L2/L3 Ready, L2 and L3. Moreover, the PEX8603 supports Vaux along with the external signal WAKE# and the in-band Beacon for the PCIe endpoints to use to inform the system host to exit the low power savings mode. ...

Page 2

... Figure 3. Modem Set-top Box Block Diagram Fan-Out The PEX8603 can be used fan-out switch to provide additional x1ports. The PEX8603 SerDes can function at 2.5GT Bandwidth Bridge There are three PCIe lanes available in the PEX8603. Each one can represent an individual port or alternatively two can be joined to form a x2 port ...

Page 3

... PEX8603 which plugs right into your system. The PEX8603 RDK can be used to test and validate customer software, or used as an evaluation vehicle for PEX8603 features and benefits. The PEX8603 RDK provides everything that a user needs to get their hardware and software development started. Manual Reset Figure 6 ...

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