74ACTQ273SJ_Q Fairchild Semiconductor, 74ACTQ273SJ_Q Datasheet

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74ACTQ273SJ_Q

Manufacturer Part Number
74ACTQ273SJ_Q
Description
Flip Flops Oct D-Type Flip-Flop
Manufacturer
Fairchild Semiconductor
Datasheet

Specifications of 74ACTQ273SJ_Q

Number Of Circuits
8
Logic Family
74ACT
Logic Type
D-Type Flip-Flop
Polarity
Non-Inverting
Input Type
Single-Ended
Propagation Delay Time
8.5 ns
High Level Output Current
- 24 mA
Supply Voltage - Max
5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SOP-20
Minimum Operating Temperature
- 40 C
Number Of Input Lines
8
Number Of Output Lines
8
Supply Voltage - Min
4.5 V
©1989 Fairchild Semiconductor Corporation
74ACTQ273 Rev. 1.4
FACT™, FACT Quiet Series™, and GTO™ are trademarks of Fairchild Semiconductor Corporation.
74ACTQ273
Quiet Series Octal D-Type Flip-Flop
Features
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagram
74ACTQ273SC
74ACTQ273SJ
74ACTQ273MTC
Order Number
I
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Guaranteed pin-to-pin skew AC performance
Improved latch-up immunity
Buffered common clock and asynchronous master
reset
Outputs source/sink 24mA
4kV minimum ESD immunity
CC
reduced by 50%
Package
Number
MTC20
M20B
M20D
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
General Description
The ACTQ273 has eight edge-triggered D-type flip-flops
with individual D inputs and Q outputs. The common
buffered Clock (CP) and Master Reset (MR) input load
and reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each
D-type input, one setup time before the LOW-to-HIGH
clock transition, is transferred to the corresponding flip-
flop's Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output
only is required and the Clock and Master Reset are
common to all storage elements.
The ACTQ utilizes Fairchild Quiet Series™ technology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Series™ features
GTO™ output control and undershoot corrector in addi-
tion to a split ground bus for superior performance.
Pin Description
D
MR
CP
Q
0
0
–D
–Q
Package Description
Pin Names
7
7
Data Inputs
Master Reset
Clock Pulse Input
Data Outputs
Description
www.fairchildsemi.com
May 2007
tm

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74ACTQ273SJ_Q Summary of contents

Page 1

... MTC20 Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. Connection Diagram FACT™, FACT Quiet Series™, and GTO™ are trademarks of Fairchild Semiconductor Corporation. ©1989 Fairchild Semiconductor Corporation 74ACTQ273 Rev. 1.4 General Description The ACTQ273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs ...

Page 2

... Logic Symbols IEEE/IEC Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1989 Fairchild Semiconductor Corporation 74ACTQ273 Rev. 1.4 Mode Select-Function Table Inputs Operating Mode MR CP Reset (Clear Load “1” ...

Page 3

... Symbol V Supply Voltage CC V Input Voltage I V Output Voltage O T Operating Temperature A ∆ ∆ t Minimum Input Edge Rate: V from 0.8V to 2.0V ©1989 Fairchild Semiconductor Corporation 74ACTQ273 Rev. 1.4 Parameter Parameter @ 4.5V, 5. Rating –0.5V to +7.0V –20mA +20mA –0. 0.5V CC –20mA +20mA –0. 0.5V CC ± ...

Page 4

... Maximum test duration 2.0ms, one output loaded at a time. 3. Max number of outputs defined as (n). n–1 Data inputs are driven 0V to 3V; one output @ GND. 4. Max number of Data Inputs (n) switching. (n–1) Inputs switching (ACTQ). Input-under-test switching threshold ( threshold (V ILD ©1989 Fairchild Semiconductor Corporation 74ACTQ273 Rev. 1.4 = +25° ...

Page 5

... Clock Pulse Width, HIGH or LOW Pulse Width, HIGH or LOW W t Recovery Time Note: 7. Voltage range 5.0 is 5.0V ± 0.5V. Capacitance Symbol Parameter C Input Capacitance IN C Power Dissipation Capacitance PD ©1989 Fairchild Semiconductor Corporation 74ACTQ273 Rev. 1.4 = +25° 50pF C L (5) V (V) Min. Typ. CC 5.0 125 189 5.0 1.5 6 ...

Page 6

... V are measured with respect to ground OHV OLP reference. 9. Input pulses have the following characteristics 1MHz 3ns 3ns, skew < 150ps Figure 1. Quiet Output Noise Voltage Waveforms ©1989 Fairchild Semiconductor Corporation 74ACTQ273 Rev. 1 and OLP OLV OHP OHV ■ ...

Page 7

... Physical Dimensions Dimensions are in inches (millimeters) unless otherwise noted. Figure 3. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide ©1989 Fairchild Semiconductor Corporation 74ACTQ273 Rev. 1.4 Package Number M20B 7 www.fairchildsemi.com ...

Page 8

... Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 4. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide ©1989 Fairchild Semiconductor Corporation 74ACTQ273 Rev. 1.4 Package Number M20D 8 www.fairchildsemi.com ...

Page 9

... Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 5. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide ©1989 Fairchild Semiconductor Corporation 74ACTQ273 Rev. 1.4 Package Number MTC20 9 www.fairchildsemi.com ...

Page 10

... TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended exhaustive list of all such trademarks. ® ACEx Across the board. Around the world.™ ActiveArray™ Bottomless™ Build it Now™ CoolFET™ ...

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