MAX7349AEG-T Maxim Integrated, MAX7349AEG-T Datasheet - Page 7

• Manufacturer Part Number: MAX7349AEG-T
• Description: Peripheral Drivers & Components - PCIs Low-EMI Key Switch & Sounder Controller
• Manufacturer: Maxim Integrated

Figure 1. Keys Order
STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission.
One data bit is transferred during each clock pulse
(Figure 4). The data on SDA must remain stable while
SCL is high.
The acknowledge bit is a clocked 9th bit (Figure 5),
which the recipient uses to handshake receipt of each
COL7/PORT7**
COL6/PORT6**
COL5/PORT5**
*MAX7348 AND
**MAX7349 ONLY.
COL4/PORT4*
COL3/PORT3*
MAX7349 ONLY.
COL2/PORT2
ROW0
ROW1
ROW2
ROW3
ROW4
ROW5
ROW6
ROW7
COL1
COL0
_______________________________________________________________________________________
2-Wire Interfaced Low-EMI Key Switch
Acknowledge
Bit Transfer
KEY
KEY
KEY
KEY
KEY
KEY
KEY
KEY
0
1
2
3
4
5
6
7
KEY
KEY
KEY
KEY
KEY
KEY
KEY
KEY
10
11
12
13
14
15
8
9
KEY
KEY
KEY
KEY
KEY
KEY
KEY
KEY
and Sounder Controllers
16
17
18
19
20
21
22
23
byte of data. Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse, so the SDA line is stable low
during the high period of the clock pulse. When the
master is transmitting to the MAX7347/MAX7348/
MAX7349, the MAX7347/MAX7348/MAX7349 generate
the acknowledge bit because the MAX7347/MAX7348/
MAX7349 are the recipients. When the MAX7347/
MAX7348/MAX7349 are transmitting to the master, the
master generates the acknowledge bit because the
master is the recipient.
KEY
KEY
KEY
KEY
KEY
KEY
KEY
KEY
24
25
26
27
28
29
30
31
KEY
KEY
KEY
KEY
KEY
KEY
KEY
KEY
32
33
34
35
36
37
38
39
KEY
KEY
KEY
KEY
KEY
KEY
KEY
KEY
40
41
42
43
44
45
46
47
KEY
KEY
KEY
KEY
KEY
KEY
KEY
KEY
48
49
50
51
52
53
54
55
KEY
KEY
KEY
KEY
KEY
KEY
KEY
KEY
56
57
58
59
60
61
62
63
7