24AA014H-I/ST Microchip Technology, 24AA014H-I/ST Datasheet - Page 11

• Manufacturer Part Number: 24AA014H-I/ST
• Description: IC EEPROM 1KBIT 400KHZ 8TSSOP
• Manufacturer: Microchip Technology

Specifications of 24AA014H-I/ST

• Memory Size: 1K (128 x 8)
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 100kHz, 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-TSSOP
• Memory Configuration: 128 X 8 / 64 X 16
• Ic Interface Type: I2C
• Clock Frequency: 400kHz
• Supply Voltage Range: 1.7V To 5.5V
• Memory Case Style: TSSOP
• No. Of Pins: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.0
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to ‘1’. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1
The 24AA014H/24LC014H contains an address coun-
ter that maintains the address of the last word
accessed, internally incremented by one. Therefore, if
the previous read access was to address n, the next
current address read operation would access data from
address n + 1. Upon receipt of the slave address with
the R/W bit set to ‘1’, the 24AA014H/24LC014H issues
an acknowledge and transmits the 8-bit data word. The
master will not acknowledge the transfer, but does
generate a Stop condition and the 24AA014H/
24LC014H discontinues transmission (Figure 8-1).
8.2
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is done by sending the word address to the
24AA014H/24LC014H as part of a write operation.
FIGURE 8-1:
© 2008 Microchip Technology Inc.
READ OPERATIONS
Current Address Read
Random Read
CURRENT ADDRESS READ
Bus Activity
Master
SDA Line
Bus Activity
S
A
R
T
T
S
Preliminary
Control
Byte
24AA014H/24LC014H
C
A
K
Once the word address is sent, the master generates a
Start condition following the acknowledge. This
terminates the write operation, but not before the
internal Address Pointer is set. The master then issues
the control byte again but with the R/W bit set to a ‘1’.
The
acknowledge and transmits the eight-bit data word.
The master will not acknowledge the transfer, but does
generate a Stop condition and the 24AA014H/
24LC014H discontinues transmission (Figure 8-2).
After this command, the internal address counter will
point to the address location following the one that was
just read.
8.3
Sequential reads are initiated in the same way as a
random read except that after the 24AA014H/
24LC014H transmits the first data byte, the master
issues an acknowledge as opposed to a Stop condition
in a random read. This directs the 24AA014H/
24LC014H to transmit the next sequentially addressed
8-bit word (Figure 8-3).
To provide sequential reads the 24AA014H/24LC014H
contains an internal Address Pointer which is
incremented by one at the completion of each
operation. This Address Pointer allows the entire
memory contents to be serially read during one
operation.
automatically roll over from address 07Fh to address
000h.
Data
24AA014H/24LC014H
Sequential Read
The
O
K
N
A
C
O
P
S
T
P
internal
Address
will
DS22077B-page 11
then
Pointer
issue
will
an