MAX1883EUP-T Maxim Integrated, MAX1883EUP-T Datasheet - Page 31

• Manufacturer Part Number: MAX1883EUP-T
• Description: LCD Drivers Quad-Output TFT LCD DC-DC Converter with Buffer
• Manufacturer: Maxim Integrated

Specifications of MAX1883EUP-T

• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Package / Case: TSSOP-20
• Mounting Style: SMD/SMT

A linear regulator’s minimum input-to-output voltage dif-
ferential (dropout voltage) determines the lowest use-
able supply voltage. Because the MAX1778/
MAX1881/MAX1883/MAX1884 use an internal pnp tran-
sistor (or external npn transistor), their dropout voltage
is a function of the transistor’s collector-to-emitter satu-
ration
Characteristics ). The linear regulator’s quiescent cur-
rent increases when in dropout.
The internal linear regulator tries to start up once its
supply voltage (V
regulator powers up, the linear regulator may be in
dropout if the linear regulator’s output set voltage is
higher than its input supply voltage. Therefore, during
this brief period, the linear regulator draws additional
supply current until the input supply voltage exceeds
the output set voltage plus the pass transistor’s satura-
tion voltage (V
The positive input (BUF+) features dual-mode opera-
tion. Connect BUF+ to GND for the preset V
put voltage, set by an internal 50% resistive-divider.
Adjust the amplifier’s output voltage by connecting a
Maxim Integrated
Figure 7. External Linear Regulator
Buffer Output Voltage and Capacitor Selection
Input-to-Output (Dropout) Voltage and Startup
voltage
LDO(SET
V
Transconductance Amplifier)
IN
SUPL
INPUT
= 3.3V
(see
VCOM Buffer (Operational
) + V
) exceeds 4V. When the linear
4.7µF
C
IN
CE(SAT)
the
0.22µF
0.22µF
C
Typical
C1
REF
).
INTG
REF
SHDN
IN
PGND
MAX1778/MAX1880–MAX1885
Operating
SUPB
(MAX1881)*
(MAX1884)*
MAX1778
MAX1883
Quad-Output TFT LCD DC/DC
6.8µH
L1
/2 out-
LDOOUT
SUPL
GND
FBL
LX
FB
voltage-divider from SUPB to BUF+ to GND (Figure 6).
Select R12 in the 10kΩ to 100kΩ range. Calculate R11
with the following equation:
where V
can range from 1.2V to (V
mum 1µF ceramic capacitor from BUFOUT to ground.
Careful PCB layout is extremely important for proper
operation. Follow the following guidelines for good PCB
layout:
1) Place the main step-up converter output diode and
2) Separate analog ground and power ground. The
Converters with Buffer
49.9kΩ
R5
1.5kΩ
274kΩ
output capacitor less than 0.2in (5mm) from the LX
and PGND pins with wide traces and no vias.
ground connections for the step-up converter’s and
charge pump’s input and output capacitors should
be connected to the power ground plane. The lin-
ear regulator’s and VCOM buffer’s input and output
capacitors should be connected to a separate
power-ground path, star-connected to the PGND
pin to minimize voltage drops. When using multi-
R1
R2
SUPB
C
4.7µF
0.01µF
0.01µF
LDOOUT
C2
C3
R
can range from 4.5V to 13V, and V
11
=
PCB Layout and Grounding
R
C
(2) 4.7µF
12
Q1
OUT
R3
49.9kΩ
R4
49.9kΩ
⎡
⎢
⎢
⎣
C
⎛
⎜
⎝
SUPB
1µF
LDOIN
V
V
SUPB
BUF
MAIN
V
MAIN
- 1.2V). Connect a mini-
+
= 8V
C
1µF
⎞
⎟
⎠
LDO
-
1
⎤
⎥
⎥
⎦
LDO
V
LDO
= 2.5V
BUF+
31