MAX6954APL+ Maxim Integrated, MAX6954APL+ Datasheet - Page 25

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MAX6954APL+

Manufacturer Part Number
MAX6954APL+
Description
LED Display Drivers Integrated Circuits (ICs)
Manufacturer
Maxim Integrated
Datasheet

Specifications of MAX6954APL+

Number Of Digits
16
Number Of Segments
128
Mounting Style
Through Hole
Package / Case
PDIP-40
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Supply Current
30 mA
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
High Level Output Current
55 mA
Low Level Output Current
935 mA
Power Dissipation
1333 mW
Factory Pack Quantity
10
Table 16. Configuration Register Format
Table 18. Blink Rate Selection (B Data Bit D2) Format
Table 19. Global Blink Enable/Disable (E Data Bit D3) Format
Table 20. Digit Register Mapping with Blink Globally Enabled
Table 21. Global Blink Timing Synchronization (T Data Bit D4) Format
Table 22. Global Clear Digit Data (R Data Bit D5) Format
Configuration
Register
Digit data for both planes P0 and P1 are unaffected.
Digit data for both planes P0 and P1 are cleared on the rising edge of CS.
Blink function is disabled.
Blink function is enabled.
Blink timing counters are unaffected.
Blink timing counters are reset on the rising edge of CS.
Slow blinking. Segments blink on for 1s, off for 1s with f
Fast blinking. Segments blink on for 0.5s, off for 0.5s with f
MODE
SEGMENT’S BIT SETTING
4-Wire Interfaced, 2.7V to 5.5V LED Display
IN PLANE P1
D7
P
MODE
______________________________________________________________________________________
0
0
1
1
D6
I
Driver with I/O Expander and Key Scan
D5
R
REGISTER DATA
MODE
MODE
D4
MODE
T
D3
E
D2
B
D7
SEGMENT’S BIT SETTING
P
P
D1
X
OSC
IN PLANE P0
D0
OSC
S
= 4MHz.
D6
I
I
0
1
0
1
= 4MHz.
Table 17. Shutdown Control (S Data Bit DO)
Format
Shutdown
Normal
Operation
D5
D7
R
R
P
P
MODE
D7
D6
P
P
REGISTER DATA
I
I
D7
D4
P
P
T
T
Segment off.
Segment on only during the 1st half of each
blink period.
Segment on only during the 2nd half of each
blink period.
Segment on.
D6
D7
P
P
I
I
D5
R
R
D6
I
I
REGISTER DATA
D6
D5
I
I
D3
0
1
0
1
D5
R
R
D4
REGISTER DATA
0
1
REGISTER DATA
D5
R
R
REGISTER DATA
D4
T
T
D4
T
T
BEHAVIOR
SEGMENT
D3
D2
D4
E
E
B
B
T
T
D3
E
E
D3
E
E
D3
E
E
D2
B
B
D2
D2
B
B
D1
0
1
X
X
D2
B
B
D1
X
X
D1
D1
X
X
X
X
D1
X
X
D0
S
S
D0
D0
D0
S
S
D0
S
S
S
S
0
1
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