IS31FL3218-QFLS2-TR ISSI, IS31FL3218-QFLS2-TR Datasheet - Page 6

• Manufacturer Part Number: IS31FL3218-QFLS2-TR
• Description: LED Lighting Drivers 18-Ch LED Drvr
• Manufacturer: ISSI

Specifications of IS31FL3218-QFLS2-TR

• Operating Frequency: 400 kHz
• Maximum Supply Current: 5.25 mA
• Output Current: 38 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-24
• Factory Pack Quantity: 2500

IS31FL3218
DETAILED DESCRIPTION
I2C INTERFACE
The IS31FL3218 uses a serial bus, which conforms to
the I2C protocol, to control the chip’s functions with two
wires: SCL and SDA. The IS31FL3218’s slave address
is “1010 1000”. It only supports write operations.
The SCL line is uni-directional. The SDA line is
bi-directional (open-collector) with a pull-up resistor
(typically 4.7kΩ). The maximum clock frequency
specified by the I2C standard is 400kHz. In this
discussion, the master is the microcontroller and the
slave is the IS31FL3218.
The timing diagram for the I2C is shown in Figure 2.
The SDA is latched in on the stable high level of the
SCL.
should be held high.
The “START” signal is generated by lowering the SDA
signal while the SCL signal is high. The start signal will
alert all devices attached to the I2C bus to check the
incoming address against their own chip address.
The 8-bit chip address is sent next, most significant bit
first. Each address bit must be stable while the SCL
level is high.
After the last bit of the chip address is sent, the master
checks for the IS31FL3218’s acknowledge. The master
releases the SDA line high (through a pull-up resistor).
Integrated Silicon Solution, Inc. – www.issi.com
Rev.B, 03/28/2012
When there is no interface activity, the SDA line
SDA
SCL
DATA LINE STABLE;
DATA VALID
Figure 4 Writing to IS31FL3218(Typical)
Figure 2 Interface timing
Figure 3 Bit transfer
CHANGE OF DATA
ALLOWED
Then the master sends an SCL pulse. If the
IS31FL3218 has received the address correctly, then it
holds the SDA line low during the SCL pulse. If the SDA
line is not low, then the master should send a “STOP”
signal (discussed later) and abort the transfer.
Following acknowledge of IS31FL3218, the register
address byte is sent, most significant bit first.
IS31FL3218 must generate another acknowledge
indicating that the register address has been received.
Then 8-bit of data byte are sent next, most significant
bit first. Each data bit should be valid while the SCL
level is stable high. After the data byte is sent, the
IS31FL3218 must generate another acknowledge to
indicate that the data was received.
The “STOP” signal ends the transfer. To signal “STOP”,
the SDA signal goes high while the SCL signal is high.
ADDRESS AUTO INCREMENT
To write multiple bytes of data into IS31FL3218, load
the address of the data register that the first data byte
is intended for. During the IS31FL3218 acknowledge of
receiving the data byte, the internal address pointer will
increment by one. The next data byte sent to
IS31FL3218 will be placed in the new address, and so
on. The auto increment of the address will continue as
long as data continues to be written to IS31FL3218
(Figure 5).
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