25LC040-I/SN Microchip Technology, 25LC040-I/SN Datasheet - Page 11
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25LC040-I/SN
Manufacturer Part Number
25LC040-I/SN
Description
IC EEPROM 4KBIT 2MHZ 8SOIC
Manufacturer
Microchip Technology
Datasheet
1.25LC040SN.pdf
(22 pages)
Specifications of 25LC040-I/SN
Memory Size
4K (512 x 8)
Package / Case
8-SOIC (3.9mm Width)
Operating Temperature
-40°C ~ 85°C
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Speed
2MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.5 V ~ 5.5 V
Organization
512 x 8
Interface Type
SPI
Maximum Clock Frequency
2 MHz
Access Time
230 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.5 V
Maximum Operating Current
5 mA
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
2.5 V
Package
8SOIC N
Density
4 Kb
Maximum Operating Frequency
2 MHz
Maximum Random Access Time
230 ns
Typical Operating Supply Voltage
3.3|5 V
Data Retention
200(Min) Year
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
25LC040-I/SN
Manufacturer:
MCP
Quantity:
27 464
Company:
Part Number:
25LC040-I/SN
Manufacturer:
MICROCHI
Quantity:
100
Part Number:
25LC040-I/SN
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
3.7
The following protection has been implemented to
prevent inadvertent writes to the array:
• The write enable latch is reset on power-up
• A write enable instruction must be issued to set
• After a byte write, page write or STATUS register
• CS must be set high after the proper number of
• Access to the array during an internal write cycle
• The write enable latch is reset when the WP pin is
TABLE 3-3:
© 2006 Microchip Technology Inc.
the write enable latch
write, the write enable latch is reset
clock cycles to start an internal write cycle
is ignored and programming is continued
low
High
High
Low
WP
Data Protection
WRITE-PROTECT FUNCTIONALITY MATRIX
WEL
X
0
1
Protected Blocks
Protected
Protected
Protected
25AA040/25LC040/25C040
Unprotected Blocks
3.8
The 25XX040 powers on in the following state:
• The device is in low-power Standby mode
• The write enable latch is reset
• SO is in high-impedance state
• A low level on CS is required to enter active state
(CS = 1)
Protected
Protected
Writable
Power-On State
STATUS Register
Protected
Protected
Writable
DS21204E-page 11