79RC32H434-300BCG IDT, 79RC32H434-300BCG Datasheet - Page 27

• Manufacturer Part Number: 79RC32H434-300BCG
• Description: Processors - Application Specialized
• Manufacturer: IDT

Specifications of 79RC32H434-300BCG

• Product Category: Processors - Application Specialized
• Rohs: yes
• Part # Aliases: IDT79RC32H434-300BCG

PCI
PCICLK
PCIAD[31:0],
PCIBEN[3:0],
PCIDEVSELN,
PCIFRA-
MEN,PCIIR-
DYN,
PCILOCKN,
PCIPAR, PCI-
PERRN, PCIS-
TOPN,
PCITRDY
PCIGNTN[3:0],
PCIREQN[3:0]
PCIRSTN (out-
put)
PCIRSTN
(input)
PCISERRN
PCIMUINTN
IDT RC32434
1.
2.
3.
4.
5.
6.
This PCI interface conforms to the PCI Local Bus Specification, Rev 2.2.
PCICLK must be equal to or less than two times ICLK (PCICLK <= 2(ICLK)) with a maximum PCICLK of 66 MHz.
The values for this symbol were determined by calculation, not by testing.
PCIRSTN is an output in host mode and an input in satellite mode.
To meet the PCI delay specification from reset asserted to outputs floating, the PCI reset should be logically combined with the COLDRSTN input, instead of input on PCIRSTN.
PCISERRN and PCIMUINTN use open collector I/O types.
Signal
1
4
4,5
2
6
6
Symbol
Thigh_10a,
Tslew_10a
Tpw_10d
Tpw_10e
Tper_10a
Tlow_10a
Tdz_10b
Tzd_10b
Tdz_10e
Thld_10b
Thld_10c
Tdo_10b
Tdo_10g
Tsu_10b
Tsu_10c
Tdo_10c
Thld_10f
Tsu_10f
Tdo_10f
3
3
3
3
3
Reference
PCICLK rising
PCICLK rising
PCICLK rising
PCICLK rising
PCIRSTN
Edge
falling
None
None
none
2(CLK)
6(CLK)
(CLK)
4000
15.0
Min
6.0
1.5
3.0
2.0
2.0
5.0
2.0
3.0
2.0
4.7
266MHz
—
0
0
0
Max
30.0
14.0
11.1
4.0
6.0
6.0
6.0
Table 10 PCI AC Timing Characteristics
—
—
—
—
—
—
—
—
—
—
—
2(CLK)
6(CLK)
(CLK)
4000
15.0
Min
6.0
1.5
3.0
2.0
2.0
5.0
2.0
3.0
2.0
4.7
300MHz
—
0
0
0
27 of 53
Max
30.0
14.0
11.1
4.0
6.0
6.0
6.0
—
—
—
—
—
—
—
—
—
—
—
6(CLK)
2(CLK)
(CLK)
4000
15.0
Min
6.0
1.5
3.0
2.0
2.0
5.0
2.0
3.0
2.0
4.7
350MHz
—
0
0
0
Max
30.0
14.0
11.1
4.0
6.0
6.0
6.0
—
—
—
—
—
—
—
—
—
—
—
2(CLK)
6(CLK)
(CLK)
4000
15.0
Min
6.0
1.5
3.0
2.0
2.0
5.0
2.0
3.0
2.0
4.7
400MHz
—
0
0
0
Max
30.0
14.0
11.1
4.0
6.0
6.0
6.0
—
—
—
—
—
—
—
—
—
—
—
Unit
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
66 MHz
PCI
Condi-
tions
January 19, 2006
See Figure 11.
See Figures 15
and 16
See Figure 11
Reference
Diagram
Timing