79RC32H434-400BC IDT, 79RC32H434-400BC Datasheet - Page 32

• Manufacturer Part Number: 79RC32H434-400BC
• Description: Processors - Application Specialized
• Manufacturer: IDT

Specifications of 79RC32H434-400BC

• Part # Aliases: IDT79RC32H434-400BC

EJTAG and JTAG
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST_
N
EJTAG_TMS
IDT RC32434
1.
2.
Signal
The JTAG specification, IEEE 1149.1, recommends that both JTAG_TMS and EJTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from 0 to 1.
The values for this symbol were determined by calculation, not by testing.
Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK when either JTAG_TMS or EJTAG_TMS is low, because the
TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.
1
,
1
Tper_16a
Thigh_16a,
Tlow_16a
Tsu_16b
Thld_16b
Tdo_16c
Tdz_16c
Tpw_16d
Tsu_16e
Thld_6e
Symbol
2
2
JTAG_TCK fall-
Reference
JTAG_TCK
JTAG_TCK
Edge
rising
none
none
rising
ing
25.0
10.0
25.0
Min
SCK, SDI, SDO (input)
2.4
1.0
2.0
1.0
266MHz
—
—
Figure 18 SPI AC Timing Waveform — Bit I/O Mode
Max
50.0
25.0
11.3
11.3
Table 14 JTAG AC Timing Characteristics
—
—
—
—
—
25.0
10.0
25.0
Min
2.4
1.0
2.0
1.0
—
—
300MHz
32 of 53
Max
50.0
25.0
11.3
11.3
—
—
—
—
—
25.0
10.0
25.0
Min
2.4
1.0
2.0
1.0
350MHz
—
—
Max
50.0
25.0
11.3
11.3
—
—
—
—
—
Tpw_15e
25.0
10.0
25.0
Min
2.4
1.0
2.0
1.0
400MHz
—
—
Max
50.0
25.0
11.3
11.3
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Condi-
tions
January 19, 2006
See Figure 19.
Reference
Diagram
Timing