74LVX00SJ_Q Fairchild Semiconductor, 74LVX00SJ_Q Datasheet - Page 7
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74LVX00SJ_Q
Manufacturer Part Number
74LVX00SJ_Q
Description
Logic Gates Qd 2-Input NAND Gate
Manufacturer
Fairchild Semiconductor
Datasheet
1.74LVX00MTCX_NL.pdf
(8 pages)
Specifications of 74LVX00SJ_Q
Product
NAND
Logic Family
74LVX
Number Of Gates
4
Number Of Lines (input / Output)
2 / 1
High Level Output Current
- 4 mA
Low Level Output Current
4 mA
Propagation Delay Time
13.6 ns, 9.7 ns
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SOP-14
Minimum Operating Temperature
- 40 C
Number Of Input Lines
2
Number Of Output Lines
1
©1993 Fairchild Semiconductor Corporation
74LVX00 Rev. 1.4.0
Physical Dimensions
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
A. CONFORMS TO JEDEC REGISTRATION MO-153,
B. DIMENSIONS ARE IN MILLIMETERS
E. LANDPATTERN STANDARD: SOP65P640X110-14M
D. DIMENSIONING AND TOLERANCES PER ANSI
F. DRAWING FILE NAME: MTC14REV6
AND TIE BAR EXTRUSIONS
VARIATION AB, REF NOTE 6
Y14.5M, 1982
Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
0.43 TYP
(Continued)
7
0.65
R0.09 min
0.45
1.65
1.00
R0.09min
12.00°
TOP & BOTTOM
6.10
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