71V35761S200PFG IDT, 71V35761S200PFG Datasheet
71V35761S200PFG
Specifications of 71V35761S200PFG
Related parts for 71V35761S200PFG
71V35761S200PFG Summary of contents
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... The burst mode feature offers the highest level of performance to the system designer, as the IDT71V35761 can provide four cycles of data for a single address presented to the SRAM. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence ...
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... LOW be left floating. This pin has an inte rnal pullup. Only available in BGA package. Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V35761/35781 HIGH to its lowest power consumption level. Data retention is guaranteed in Slee p Mode.This pin has an internal pull down ...
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... IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Functional Block Diagram Commercial and Industrial Temperature Ranges 6.42 3 ...
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... -55 to +125 2.0 W NOTES (max (min) = -1.0V for pulse width less than t 5301 tbl 03 IL during power supply ramp up. 119 BGA Capacitance (T = +25° 1.0MHz) A Max. Unit Symbol = 3dV 3dV 7 pF OUT ...
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... IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Pin Configuration – 128K x 36 100 DDQ DDQ ...
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... IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Pin Configuration – 128K x 36, 119 BGA DDQ I I DDQ I I DDQ DDQ N I DDQ NOTES connected to an input voltage ≥ ...
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... IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Pin Configuration – 128K x 36, 165 fBGA ( I DDQ D I/O I DDQ E I/O I DDQ F I/O I DDQ G I/O I DDQ ...
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... IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter |I | Input Leakage Current LI ZZ, LBO and JTAG Input Leakage Current |I | LZZ |I | Output Leakage Current LO V Output Low Voltage ...
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... IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Synchronous Truth Table Operation Address Used Deselected Cycle, Power Down None Deselected Cycle, Power Down None Deselected Cycle, Power Down None Deselected Cycle, Power Down None Deselected Cycle, Power Down ...
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... IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Synchronous Write Function Truth Table GW Operation Read H Read H Write all Bytes L Write all Bytes H (3) Write Byte 1 H (3) Write Byte 2 H (3) Write Byte 3 H (3) Write Byte 4 H NOTES: 1 ...
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... IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect AC Electrical Characteristics (V = 3.3V ±5%, Commercial and Industrial Temperature Ranges) DD Symbol Parameter t Clock Cycle Time CYC (1) Clock High Pulse Width t CH (1) Clock Low Pulse Width t CL Output Parameters t Clock High to Valid Data ...
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... IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Timing Waveform of Pipelined Read Cycle Commercial and Industrial Temperature Ranges (1,2) , 6.42 12 ...
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... IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Timing Waveform of Combined Pipelined Read and Write Cycles Commercial and Industrial Temperature Ranges , 6.42 13 (1,2,3) ...
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... IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Timing Waveform of Write Cycle No Controlled Commercial and Industrial Temperature Ranges (1,2,3) 6. ...
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... IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Timing Waveform of Write Cycle No Byte Controlled Commercial and Industrial Temperature Ranges (1,2,3) 6. ...
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... IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Timing Waveform of Sleep (ZZ) and Power-Down Modes Commercial and Industrial Temperature Ranges (1,2,3) 6. ...
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... IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Non-Burst Read Cycle Timing Waveform CLK ADSP ADSC ADDRESS GW, BWE, BWx CE DATA OUT NOTES input is LOW, ADV is HIGH and LBO is Don't Care for this cycle. ...
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... IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect JTAG Interface Specification (SA Version only TCK (1) Device Inputs / TDI/TMS (2) Device Outputs / TDO ( 3) TRST t JRST NOTES: 1. Device inputs = All device inputs except TDI, TMS and TRST. 2. Device outputs = All device outputs except TDO. ...
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... IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect JTAG Identification Register Definitions (SA Version only) Instruction Field Revision Number (31:28) IDT Device ID (27:12) IDT JEDEC ID (11:1) ID Register Indicator Bit (Bit 0) Available JTAG Instructions Instruction EXTEST SAMPLE/PRELOAD DEVICE_ID HIGHZ RESERVED ...
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... IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Ordering Information Package Information 100-Pin Thin Quad Plastic Flatpack (TQFP) 119 Ball Grid Array (BGA) 165 Fine Pitch Ball Grid Array (fBGA) Information available on the IDT website Commercial and Industrial Temperature Ranges 6 ...
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... CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 The IDT logo is a registered trademark of Integrated Device Technology, Inc. Created new datasheet from 71v3576 and 71v3578 datasheet. Added industrial temperature range offering from 166MHz and 183MHz Added 100 pin TQFP package Diagram Outline Add BGA capacitance table ...