7025L20JGI IDT, 7025L20JGI Datasheet
7025L20JGI
Specifications of 7025L20JGI
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7025L20JGI Summary of contents
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... BUSY outputs and INT outputs are non-tri-stated push-pull. ©2012 Integrated Device Technology, Inc. HIGH-SPEED DUAL-PORT STATIC RAM IDT7025 easily expands data bus width to 32 bits or more ◆ ◆ ◆ ◆ ◆ using the Master/Slave select when cascading more than one device ◆ ◆ ◆ ◆ ◆ ...
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... High-Speed Dual-Port Static RAM Description The IDT7025 is a high-speed Dual-Port Static RAM. The IDT7025 is designed to be used as a stand-alone 128K-bit Dual-Port RAM combination MASTER/SLAVE Dual-Port RAM for 32-bit or more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-bit or wider memory system applications results in full-speed, error- free operation without the need for additional discrete logic ...
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... OE SEM I/O I/O I I/O I/O I R/W GND IDT7025G (4) G84-3 74 GND 84-Pin PGA (5) Top View SEM GND GND I/O I/O I/O R/W 10R 13R 15R ...
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... IDT7025S/L High-Speed Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Pin Names Left Port Right Port R/W R 12L 0R 12R I/O - I/O I/O - I/O 0L 15L 0R 15R SEM SEM INT INT L R BUSY BUSY ...
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... IDT7025S/L High-Speed Dual-Port Static RAM Truth Table I: Non-Contention Read/Write Control (1) Inputs R NOTE — A ≠ A — 12L 0R 12R. Truth Table II: Semaphore Read/Write Control ...
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... Recommended DC Operating Conditions Symbol > Vcc + 10%. TERM V CC GND (2) Max. Unit NOTES 3dV > -1.5V for pulse width less than 10ns 3dV 10 pF TERM OUT 2683 tbl 07 (V Test Conditions V = 5.5V OUT CC ...
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... IDT7025S/L High-Speed Dual-Port Static RAM DC Electrical Characteristics Over the 0perating Temperature and Supply Voltage Range Symbol Parameter Test Condition I Dynamic Operating Outputs Disabled CC IL Current SEM = V IH (Both Ports Active) ( MAX I Standby Current = SB1 L R (Both Ports - TTL ...
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... IDT7025S/L High-Speed Dual-Port Static RAM Data Retention Characteristics Over All Temperature Ranges (L Version Only) Symbol Parameter V V for Data Retention Data Retention Current CCDR (3) t Chip Dese lect to Data Retention Time CDR (3) t Operation Recovery Time R NOTES +25° 2V, and are not production tested ...
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... IDT7025S/L High-Speed Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter READ CYCLE t Read Cycle Time RC t Address Access Time AA t (3) Chip Enable Access Time ACE (3) t Byte Enable Access Time ABE t (3) Output Enable Access Time ...
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... IDT7025S/L High-Speed Dual-Port Static RAM Waveform of Read Cycles ADDR CE OE UB, LB R/W DATA OUT BUSY OUT NOTES: 1. Timing depends on which signal is asserted last, OE, CE, LB, or UB. 2. Timing depends on which signal is de-asserted first, CE, OE, LB delay is required only in case where opposite port is completing a write operation to the same address location for simultaneous read operations BUSY BDD has no relation to valid output data ...
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... WRITE CYCLE t Write Cycle Time WC (3) t Chip Enable to End-of-Write EW t Address Valid to End-of-Write AW (3) t Address Set-up Time AS t Write Pulse Width WP t Write Recovery Time WR t Data Valid to End-of-Write DW (1,2) t Output High-Z Time HZ (4) t Data Hold Time DH (1,2) ...
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... This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with Output Test Load (Figure 2 during R/W controlled write cycle, the write pulse width must be the larger placed on the bus for the required ...
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... IDT7025S/L High-Speed Dual-Port Static RAM Timing Waveform of Semaphore Read after Write Timing, Either Side VALID ADDRESS t AW SEM DATA R/W OE Write Cycle NOTE & for the duration of the above timing (both write and read cycle). ...
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... IDT7025S/L High-Speed Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature Supply Voltage Range Symbol Parameter BUSY TIMING (M BUSY Access Time from Address Match BAA t BUSY Disable Time from Address Not Matched BDA t BUSY Access Time from Chip Enable LOW ...
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... IDT7025S/L High-Speed Dual-Port Static RAM Timing Waveform of Write Port-to-Port Read and BUSY ADDR "A" R/W "A" DATA IN "A" (1) t APS ADDR "B" BUSY "B" DATA OUT "B" NOTES ensure that the earlier of the two ports wins ...
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... IDT7025S/L High-Speed Dual-Port Static RAM Waveform of BUSY Arbitration Controlled by CE Timing ADDR "A" and "B" CE "A" (2) t APS CE "B" BUSY "B" Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing (M (1) IH ADDR "A" t APS ADDR " ...
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... IDT7025S/L High-Speed Dual-Port Static RAM Waveform of Interrupt Timing ADDR "A" ( "A" R/W "A" INT "B" ADDR "B" "B" OE "B" INT "B" NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. ...
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... NOTES: 1. Pins BUSY and BUSY are both outputs when the part is configured as a master. BUSY are inputs when configured as a slave. BUSYx outputs on the IDT7025 L R are push pull, not open drain outputs. On slaves the BUSY asserted internally inhibits write. 2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and enable inputs of this port ...
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... BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the BUSY signal as a write inhibit signal. Thus on the IDT7025 RAM the BUSY pin is an output if the part is used as a master (M/S pin = V the BUSY pin is an input if the part used as a slave (M/S pin = V in Figure 3 ...
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... Using Semaphores—Some Examples Perhaps the simplest application of semaphores is their application as resource markers for the IDT7025’s Dual-Port RAM. Say the RAM was to be divided into two blocks which were to be dedicated at any one time to servicing either the left or right port. Semaphore 0 could ...
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... This allows the interpreting processor to come back and read the complete data structure, thereby guaranteeing a consistent data structure. SEMAPHORE SEMAPHORE REQUEST FLIP FLOP REQUEST FLIP FLOP READ Figure 4. IDT7025 Semaphore Logic 6. PORT WRITE SEMAPHORE READ . ...
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... Page 22 Removed "IDT" from orderable part number 07/17/12: Page 22 Added T&R and green indicators to ordering information CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 The IDT logo is a registered trademark of Integrated Device Technology, Inc. Military, Industrial and Commercial Temperature Ranges Process/ ...