71256SA15TPG IDT, 71256SA15TPG Datasheet - Page 6

• Manufacturer Part Number: 71256SA15TPG
• Description: SRAM 32Kx8 ASYNCHRONOUS 5.0V STATIC RAM
• Manufacturer: IDT
• Series: IDT71256SAr
• Type: Asyncronous Static RAMr

Specifications of 71256SA15TPG

• Rohs: yes
• Memory Size: 256 kbit
• Organization: 32 K x 8
• Access Time: 15 ns
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V
• Maximum Operating Current: 150 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Package / Case: PDIP-28
• Memory Type: CMOS
• Part # Aliases: IDT71256SA15TPG

Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)
NOTES:
1. A write occurs during the overlap of a LOW CS and a LOW WE.
2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, t
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
IDT71256SA
CMOS Static RAM 256K (32K x 8-Bit)
to be placed on the bus for the required t
short as the specified t
ADDRESS
ADDRESS
DATA
DATA
DATA
OUT
WE
WE
CS
CS
IN
IN
WP
.
t
t
AS
(3)
AS
DW
. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as
t
WHZ
(5)
t
t
AW
AW
t
t
WP
t
t
WC
CW
WC
WP
HIGH IMPEDANCE
(2)
must be greater than or equal to t
6
t
DW
DATA
t
DW
DATA
IN
VALID
Commercial and Industrial Temperature Ranges
IN
VALID
t
DH
t
t
WR
t
OW
WR
WHZ
(5)
t
DH
+ t
DW
to allow the I/O drivers to turn off and data
(3)
t
CHZ
(1,4)
(1,2,4)
(5)
2948 drw 08
2948 drw 07
,
,