7005S55J IDT, 7005S55J Datasheet
7005S55J
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7005S55J Summary of contents
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... IDT7005S Active: 750mW (typ.) Standby: 5mW (typ.) – IDT7005L Active: 700mW (typ.) Standby: 1mW (typ.) IDT7005 easily expands data bus width to 16 bits or more ◆ using the Master/Slave select when cascading more than one device Functional Block Diagram ...
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... IDT7005S/L High-Speed Dual-Port Static RAM Description The IDT7005 is a high-speed Dual-Port Static RAM. The IDT7005 is designed to be used as a stand-alone 64K-bit Dual-Port RAM combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider memory system applications results in full-speed, error- free operation without the need for additional discrete logic ...
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... Military, Industrial and Commercial Temperature Ranges (con't BUSY INT M INT GND BUSY IDT7005G G68-1 (4) 68-Pin PGA Top View ( GND I/O GND I/O I I/O I/O V I/O I/O I ...
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... Recommended DC Operating Conditions Symbol V CC > Vcc + 10%. TERM GND V IH (2) Max. Unit 3dV NOTES > -1.5V for pulse width less than 10ns 3dV TERM 2738 tbl 07 6.42 4 Mode (1) Mode - (1,2) Ambient Temperature GND -55 C to+125 C ...
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... IDT7005S/L High-Speed Dual-Port Static RAM DC Electrical Characteristics Over the 0perating Temperature and Supply Voltage Range Symbol Parameter ( Input Leakage Current Output Leakage Current LO V Output Low Voltage OL V Output High Voltage OH NOTE Vcc < 2.0V input leakages are undefined. ...
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... IDT7005S/L High-Speed Dual-Port Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter I Dynamic Operating Current Outputs Disabled CC IL (Both Ports Active) SEM = MAX I Standby Current SB1 = (Both Ports - TTL = SEM ...
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... IDT7005X70 Com'l, Ind Com'l, Ind Military & Military & Military Only Min. Max. Min. Max. Min. Max ____ ____ ____ ____ ____ ...
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... IDT7005S/L High-Speed Dual-Port Static RAM Waveform of Read Cycles ADDR CE OE R/W DATA OUT BUSY OUT NOTES: 1. Timing depends on which signal is asserted last CE. 2. Timing depends on which signal is de-asserted first delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY BDD has no relation to valid output data ...
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... Symbol WRITE CYCLE t Write Cycle Time WC (3) t Chip Enable to End-of-Write EW t Address Valid to End-of-Write AW (3) t Address Set-up Time AS t Write Pulse Width WP t Write Recovery Time WR t Data Valid to End-of-Write DW (1,2) t Output High-Z Time HZ (4) t Data Hold Time DH t ...
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... This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 2 LOW during R/W controlled write cycle, the write pulse width must be the larger the bus for the required t ...
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... IDT7005S/L High-Speed Dual-Port Static RAM Timing Waveform of Semaphore Read after Write Timing, Either Side VALID ADDRESS SEM DATA R/W OE Write Cycle NOTE for the duration of the above timing (both write and read cycle). IH Timing Waveform of Semaphore Write Contention ...
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... IDT7005S/L High-Speed Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter BUSY TIMING (M/S BUSY Access Time from Address Match BAA t BUSY Disable Time from Address Not Matched BDA t BUSY Access Time from Chip Enable Low ...
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... IDT7005S/L High-Speed Dual-Port Static RAM Timing Waveform of Write with Port-to-Port Read with BUSY (M (4) IH ADDR "A" R/W "A" DATA IN "A" (1) t APS ADDR "B" BUSY "B" DATA OUT "B" NOTES ensure that the earlier of the two ports wins ...
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... IDT7005S/L High-Speed Dual-Port Static RAM Waveform of BUSY Arbitration Controlled by CE Timing ADDR "A" and "B" CE "A" (2) t APS CE "B" BUSY "B" Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing (M (1) IH ADDR "A" t APS ADDR " ...
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... IDT7005S/L High-Speed Dual-Port Static RAM Waveform of Interrupt Timing ADDR "A" ( "A" R/W "A" INT "B" ADDR "B" "B" OE "B" INT "B" NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. ...
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... Right Port Writes "1" to Semaphore Left Port Writes "0" to Semaphore Left Port Writes "1" to Semaphore NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7005. 2. There are eight semaphore flags written to via I/O 3. CE=V , SEM=V to access the semaphores. Refer to the semaphore Read/Write Control Truth Table. ...
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... IDT7005S/L High-Speed Dual-Port Static RAM BUSY (L) Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7005 RAMs. Busy Logic Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is “ ...
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... Using Semaphores—Some Examples Perhaps the simplest application of semaphores is their application as resource markers for the IDT7005’s Dual-Port RAM. Say the RAM was to be divided into two blocks which were to be dedicated at any one time to servicing either the left or right port. Semaphore 0 could be used to indicate the side which would control the lower section of memory, and 6 ...
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... When the update is completed, the data structure block is released. This allows the interpreting processor to come back and read the complete data structure, thereby guaranteeing a consistent data structure. SEMAPHORE REQUEST FLIP FLOP READ Figure 4. IDT7005 Semaphore Logic 6. PORT SEMAPHORE WRITE ...
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... Dual-Port RAM Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Added additional notes to pin configurations Changed drawing format Replaced IDT logos Added copywright info Fixed overbar errors Increated storage temperature parameter Clarified T Parameter A DC Electrical parameters–changed wording from "open" to "disabled" ...
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... Page 20 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 The IDT logo is a registered trademark of Integrated Device Technology, Inc. Military, Industrial and Commercial Temperature Ranges Added green availability to features Added green indicator to ordering information Removed "IDT" from orderable part number In all of the DC & ...