CAT1026WI-25-G ON Semiconductor, CAT1026WI-25-G Datasheet - Page 12

• Manufacturer Part Number: CAT1026WI-25-G
• Description: Supervisory Circuits CPU w/2K
• Manufacturer: ON Semiconductor

Specifications of CAT1026WI-25-G

• Product Category: Supervisory Circuits
• Rohs: yes
• Number Of Voltages Monitored: 1
• Monitored Voltage: 3 V, 3.3 V, 5 V
• Undervoltage Threshold: 2.55 V
• Overvoltage Threshold: 2.7 V
• Manual Reset: Not Resettable
• Watchdog: No Watchdog
• Supply Voltage - Max: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8 Wide
• Maximum Power Dissipation: 1000 mW
• Minimum Operating Temperature: - 40 C
• Supply Current (typ): 3000 uA
• Supply Voltage - Min: 2.7 V

Immediate/Current Address Read
address of the last byte accessed, incremented by one. In
other words, if the last READ or WRITE access was to
address N, the READ immediately following would access
data from address N + 1. For N = E = 255, the counter will
wrap around to zero and continue to clock out valid data.
After the CAT1026 and CAT1027 receive its slave address
information (with the R/W bit set to one), it issues an
acknowledge, then transmits the 8−bit byte requested. The
master device does not send an acknowledge, but will
generate a STOP condition.
Selective/Random Read
device to select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte addresses of the location it wishes to read.
After the CAT1026 and CAT1027 acknowledges, the Master
device sends the START condition and the slave address
The CAT1026 and CAT1027 address counter contains the
Selective/Random READ operations allow the Master
SDA
SCL
BUS ACTIVITY:
SDA LINE
MASTER
BUS ACTIVITY:
S
S
A
R
T
T
SDA LINE
MASTER
ADDRESS
Figure 11. Immediate Address Read Timing
SLAVE
DATA OUT
8TH BIT
Figure 12. Selective Read Timing
8
S
S
A
R
T
T
A
C
K
http://onsemi.com
ADDRESS (n)
ADDRESS
SLAVE
BYTE
12
again, this time with the R/W bit set to one. The CAT1026
and CAT1027 then respond with its acknowledge and send
the 8−bit byte requested. The master device does not send an
acknowledge but will generate a STOP condition.
Sequential Read
the Immediate Address READ or Selective READ
operations. After the CAT1026 and CAT1027 sends the
initial 8− bit byte requested, the Master will respond with an
acknowledge which tells the device it requires more data.
The CAT1026 and CAT1027 will continue to output an 8−bit
byte for each acknowledge, thus sending the STOP
condition.
CAT1027 is sent sequentially with the data from address N
followed by data from address N + 1. The READ operation
address counter increments all of the CAT1026and
CAT1027 address bits so that the entire memory array can
be read during one operation.
The Sequential READ operation can be initiated by either
The data being transmitted from the CAT1026 and
A
C
K
A
C
K
NO ACK
S
A
R
S
T
T
9
ADDRESS
SLAVE
DATA
A
C
K
O
N
A
C
K
P
O
S
T
P
DATA n
STOP
N
O
A
C
K
P
O
S
T
P