CAT1641WI-28-G ON Semiconductor, CAT1641WI-28-G Datasheet - Page 12

• Manufacturer Part Number: CAT1641WI-28-G
• Description: Supervisory Circuits CPU w/64K
• Manufacturer: ON Semiconductor

Specifications of CAT1641WI-28-G

• Product Category: Supervisory Circuits
• Rohs: yes
• Number Of Voltages Monitored: 1
• Monitored Voltage: 3 V, 3.3 V, 5 V
• Undervoltage Threshold: 2.85 V
• Overvoltage Threshold: 3 V
• Output Type: Active High, Open Drain
• Manual Reset: Resettable
• Watchdog: No Watchdog
• Battery Backup Switching: No Backup
• Power-up Reset Delay (typ): 270 ms
• Supply Voltage - Max: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8 Wide
• Chip Enable Signals: No
• Maximum Power Dissipation: 1000 mW
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: No
• Supply Current (typ): 3000 uA
• Supply Voltage - Min: 3 V

Immediate/Current Address Read
address of the last byte accessed, incremented by one. In
other words, if the last READ or WRITE access was to
address N, the READ immediately following would access
data from address N+1. For all devices, N = E = 4,095. The
counter will wrap around to Zero and continue to clock out
valid data. After the CAT1640 and CAT1641 receives its
slave address information (with the R/W bit set to one), it
issues an acknowledge, then transmits the 8−bit byte
requested. The master device does not send an acknowledge,
but will generate a STOP condition.
Selective/Random Read
device to select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte addresses of the location it wishes to read.
After the CAT1640 and CAT1641 acknowledges, the Master
device sends the START condition and the slave address
The CAT1640 and CAT1641 address counter contains the
Selective/Random READ operations allow the Master
* = Don’t Care Bit
BUS ACTIVITY:
SDA LINE
MASTER
BUS ACTIVITY:
SDA LINE
MASTER
S
R
S
T
A
T
ADDRESS
ADDRESS
SLAVE
SLAVE
C
A
K
A
C
K
* **
DATA n
Figure 12. Sequential Read Timing
Figure 11. Selective Read Timing
A 15 –A 8
BYTE ADDRESS
http://onsemi.com
C
A
K
C
A
K
DATA n+1
12
A 7 –A 0
again, this time with the R/W bit set to one. The CAT1640
and CAT1641 then responds with its acknowledge and sends
the 8−bit byte requested. The master device does not send an
acknowledge but will generate a STOP condition.
Sequential Read
the Immediate Address READ or Selective READ
operations. After the CAT1640 and CAT1641 sends the
initial 8−bit byte requested, the Master will responds with an
acknowledge which tells the device it requires more data.
The CAT1640 and CAT1641 will continue to output an 8−bit
byte for each acknowledge, thus sending the STOP
condition.
CAT1641 is sent sequentially with the data from address N
followed by data from address N+1. The READ operation
address counter increments all of the CAT1640 and
CAT1641 address bits so that the entire memory array can
be read during one operation.
The Sequential READ operation can be initiated by either
The data being transmitted from the CAT1640 and
A
C
K
A
C
K
DATA n+2
R
S
T
A
T
S
ADDRESS
SLAVE
A
C
K
A
C
K
DATA n+x
DATA
N
O
C
A
K
O
S
T
P
P
N
O
A
C
K
O
P
S
T
P