CAT1163WI-25-G ON Semiconductor, CAT1163WI-25-G Datasheet - Page 9

• Manufacturer Part Number: CAT1163WI-25-G
• Description: Supervisory Circuits CPU w/16K
• Manufacturer: ON Semiconductor

Specifications of CAT1163WI-25-G

• Product Category: Supervisory Circuits
• Rohs: yes
• Number Of Voltages Monitored: 1
• Monitored Voltage: 3 V, 3.3 V, 5 V
• Undervoltage Threshold: 2.55 V
• Overvoltage Threshold: 2.7 V
• Output Type: Active High, Active Low, Open Drain
• Manual Reset: Resettable
• Watchdog: Watchdog
• Battery Backup Switching: No Backup
• Power-up Reset Delay (typ): 270 ms
• Supply Voltage - Max: 6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8 Wide
• Chip Enable Signals: No
• Maximum Power Dissipation: 1000 mW
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: No
• Supply Current (typ): 3000 uA
• Supply Voltage - Min: 2.7 V

same manner as the write operation with one exception, that
R/W bit is set to one. Three different READ operations are
possible:
Selective/Random READ and Sequential READ.
Immediate/Current Address Read
the last byte accessed, incremented by one. In other words,
Selective/Random Read
device to select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte addresses of the location it wishes to read.
After the CAT1163 acknowledges, the Master device sends
the START condition and the slave address again, this time
with the R/W bit set to one. The CAT1163 then responds
with its acknowledge and sends the 8−bit byte requested.
The master device does not send an acknowledge but will
generate a STOP condition.
Sequential Read
the Immediate Address READ or Selective READ
operations. After the CAT1163 sends the inital 8−bit byte
requested, the Master will responds with an acknowledge
which tells the device it requires more data. The CAT1163
will continue to output an 8−bit byte for each acknowledge,
thus sending the STOP condition.
sequentially with data from address N followed by data from
address N+1. The READ operation address counter
increments all of the CAT1163 address bits so that the entire
The READ operation for the CAT1163 is initiated in the
The CAT1163’s address counter contains the address of
Selective/Random READ operations allow the Master
The Sequential READ operation can be initiated by either
The data being transmitted from the CAT1163 is outputted
SDA
SCL
Immediate/Current
BUS ACTIVITY:
SDA LINE
MASTER
Address
Figure 9. Immediate Address Read Timing
DATA OUT
8TH BIT
8
S
S
A
R
T
T
READ OPERATIONS
READ,
http://onsemi.com
ADDRESS
SLAVE
9
if the last READ or WRITE access was to address N, the
READ immediately following would access data from
address N+1. If N = E (where = 2047 for the CAT1163) then
the counter will ‘wrap around’ to address 0 and continue to
clock out data. After the CAT1163 receives its slave address
information (with the R/W bit set to one), it issues an
acknowledge, then transmits the 8−bit byte requested. The
master device does not send an acknowledge, but will
generate a STOP condition.
memory array can be read during one operation. If more than
E (where E=2047 for the CAT1163) bytes are read out, the
counter will ‘wrap around’ and continue to clock out data
bytes.
Manual Reset Operation
a manual reset input.
internally sensed. The positive edge is sensed if RESET is
used as a manual reset input and the negative edge is sensed
if RESET is used as a manual reset input.
time, the complementary reset output will be kept in the
active state. If the manual reset input is forced active for
more than 200 ms, the complementary reset output will
switch back to the non active state after the 200 ms expired,
regardless for how long the manual reset input is forced
active.
condition is maintained on any RESET pin. If the external
forced RESET/RESET is longer than internal controlled
time−out period, t
an acknowledge for any access as long as the manual reset
input is active.
The CAT116x RESET or RESET pin can also be used as
Only the “active” edge of the manual reset input is
An internal counter starts a 200 ms count. During this
The embedded EEPROM is disabled as long as a reset
A
C
K
NO ACK
9
DATA
PURST
O
N
A
C
K
P
, the memory will not respond with
O
S
T
P
STOP