IS61C1024AL-12TLI ISSI, Integrated Silicon Solution Inc, IS61C1024AL-12TLI Datasheet - Page 8

• Manufacturer Part Number: IS61C1024AL-12TLI
• Description: IC SRAM 1MBIT 12NS 32TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS61C1024AL-12TLI

• Format - Memory: RAM
• Memory Type: SRAM - Asynchronous
• Memory Size: 1M (128K x 8)
• Speed: 12ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TSOP
• Density: 1Mb
• Access Time (max): 12ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 17b
• Package Type: TSOP-I
• Operating Temp Range: -40C to 85C
• Number Of Ports: 1
• Supply Current: 40mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Word Size: 8b
• Number Of Words: 128K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 706-1087; IS61C1024AL-12TLI

8
IS61C1024AL, IS64C1024AL
AC WAVEFORMS
WRITE CYCLE NO. 1
WRITE CYCLE NO. 2
Notes:
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states
2. I/O will assume the High-Z state if OE = V
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced
to the rising or falling edge of the signal that terminates the Write.
ADDRESS
ADDRESS
D
D
CE1
CE2
OUT
WE
CE1
CE2
D
OE
OUT
WE
D
IN
IN
LOW
HIGH
t
SA
(CE1 Controlled, OE is HIGH or LOW)
(OE is HIGH During Write Cycle)
DATA UNDEFINED
DATA UNDEFINED
t
SA
IH
.
Integrated Silicon Solution, Inc. — www.issi.com —
VALID ADDRESS
t
t
AW
t
HZWE
HZWE
t
VALID ADDRESS
t
AW
t
t
t
PWE1
WC
PWE1
PWE2
t
t
t
SCE1
SCE2
WC
(1,2)
HIGH-Z
HIGH-Z
(1 )
t
t
SD
DATA
SD
DATA
IN
IN
VALID
VALID
t
t
HD
t
HD
t
LZWE
LZWE
t
t
HA
HA
CE2_WR2.eps
CE2_WR1.eps
ISSI
1-800-379-4774
01/24/05
Rev. B
®