7024S55J8 IDT, 7024S55J8 Datasheet - Page 12

• Manufacturer Part Number: 7024S55J8
• Description: SRAM
• Manufacturer: IDT

Specifications of 7024S55J8

• Part # Aliases: IDT7024S55J8

Timing Waveform of Semaphore Read after Write Timing, Either Side
NOTES:
1. CE = V
2. “DATA
Timing Waveform of Semaphore Write Contention
NOTES:
1. D
2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/W
4. If t
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
0R
SPS
A
= D
SEM
R/W
0
I/O
OUT
is not satisfied, there is no guarantee which side will obtain the semaphore flag.
-A
OE
IH
0L
or UB & LB = V
2
0
VALID” represents all I/O's (I/O
= V
SIDE
SIDE
IL
, CE
(2)
(2)
R
= CE
"B"
"A"
IH
L
for the duration of the above timing (both write and read cycle).
= V
IH
, or both UB & LB = V
A
A
t
VALID ADDRESS
AS
0"A"
0"B"
A
or SEM
t
SEM
SEM
R/W
R/W
AW
-A
-A
0
-I/O
Write Cycle
2"A"
2"B"
15
"A"
"A"
"B"
"B"
A
t
t
) equal to the semaphore value.
EW
going HIGH to R/W
WP
DATA
VALID
IH
, semaphore flag is released from both sides (reads as ones from both sides) at cycle start.
t
t
DW
WR
IN
t
DH
MATCH
B
or SEM
t
SWRD
6.42
12
B
going HIGH.
MATCH
VALID ADDRESS
t
SOP
Military, Industrial and Commercial Temperature Ranges
Read Cycle
t
SAA
t
SPS
t
ACE
t
(1,3,4)
AOE
DATA
VALID
OUT
2740 drw 12
(2)
t
OH
,
2740 drw 11
(1)