71024S20YG IDT, 71024S20YG Datasheet - Page 6

• Manufacturer Part Number: 71024S20YG
• Description: SRAM 128Kx8 ASYNCHRONOUS 5.0V STATIC RAM
• Manufacturer: IDT

Specifications of 71024S20YG

• Rohs: yes
• Part # Aliases: IDT71024S20YG

Timing Waveform of Write Cycle No. 2
(CS
NOTES:
1. A write occurs during the overlap of a LOW CS
2. t
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS
5. Transition is measured ±200mV from steady state.
6. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, t
Timing Waveform of Write Cycle No. 1
(WE Controlled Timing)
IDT71024 CMOS Static RAM
1 Meg (128K x 8-Bit)
both be active during the t
on the bus for the required t
WR
is measured from the earlier of either CS
1
1
AND CS
LOW transition or the CS
CW
DW
2
write period.
. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified t
Controlled Timing)
2
HIGH transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS
1
or WE going HIGH or CS
1
, HIGH CS
(1,4,6)
2
, and a LOW WE.
2
going LOW to the end of the write cycle.
WP
(1,4)
must be greater than or equal to t
6.42
6
Commercial and Industrial Temperature Ranges
WHZ
+ t
DW
to allow the I/O drivers to turn off and data to be placed
WP
1
.
and CS
2
must