IS61WV5128BLL-10TLI ISSI, Integrated Silicon Solution Inc, IS61WV5128BLL-10TLI Datasheet - Page 12
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IS61WV5128BLL-10TLI
Manufacturer Part Number
IS61WV5128BLL-10TLI
Description
IC SRAM 4MBIT 10NS 44TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
Asynchronousr
Datasheet
1.IS61WV5128BLL-10TLI.pdf
(25 pages)
Specifications of IS61WV5128BLL-10TLI
Format - Memory
RAM
Memory Type
SRAM - Asynchronous
Memory Size
4M (512K x 8)
Speed
10ns
Interface
Parallel
Voltage - Supply
1.65 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TSOP II
Access Time
10 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.4 V
Maximum Operating Current
40 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Ports
1
Operating Supply Voltage
2.5 V, 3.3 V
Density
4Mb
Access Time (max)
10ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
2.5/3.3V
Address Bus
19b
Package Type
TSOP-II
Operating Temp Range
-40C to 85C
Supply Current
40mA
Operating Supply Voltage (min)
2.4V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Word Size
8b
Number Of Words
512K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
706-1108
IS61WV5128BLL-10TLI
Q4714568
IS61WV5128BLL-10TLI
Q4714568
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IS61WV5128BLL-10TLI
Manufacturer:
ISSI
Quantity:
675
Company:
Part Number:
IS61WV5128BLL-10TLI
Manufacturer:
PANASONIC
Quantity:
2 606
Part Number:
IS61WV5128BLL-10TLI
Manufacturer:
ISSI
Quantity:
20 000
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
WRITE CYCLE SWITCHING CHARACTERISTICS
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output load-
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one
12
Symbol
ing specified in Figure 1.
can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that
terminates the write. Shaded area product in development
Notes:
t
t
t
t
t
t
t
t
t
t
t
wC
sCe
Aw
hA
sA
Pwe
Pwe
sd
hd
hzwe
lzwe
1
2
(2)
(2)
Parameter
Write Cycle Time
CE to Write End
Address Setup Time
to Write End
Address Hold from Write End
Address Setup Time
WE Pulse Width (OE = HIGH)
WE Pulse Width (OE = LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
Min.
6.5
6.5
6.5
8.0
—
8
0
0
5
0
2
-8
Max.
3.5
—
—
—
—
—
—
—
—
—
—
(1,3)
(Over Operating Range)
Integrated Silicon Solution, Inc. — www.issi.com
Min.
10
10
—
8
8
0
0
8
6
0
2
-10
Max.
—
—
—
—
—
—
—
—
—
—
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
08/10/09
Rev. I