CY7C1021DV33-10ZSXAT Cypress Semiconductor, CY7C1021DV33-10ZSXAT Datasheet - Page 5

• Manufacturer Part Number: CY7C1021DV33-10ZSXAT
• Description: SRAM 1-Mbit 64k x16 Static RAM
• Manufacturer: Cypress Semiconductor

Specifications of CY7C1021DV33-10ZSXAT

• Rohs: yes
• Memory Size: 1 Mbit
• Organization: 64 K x 16
• Access Time: 10 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V
• Maximum Operating Current: 60 mA
• Mounting Style: SMD/SMT
• Package / Case: TSOP-44
• Memory Type: Asynchronous CMOS
• Factory Pack Quantity: 1000

Switching Characteristics
Document #: 38-05460 Rev. *G
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
power
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
DBE
LZBE
HZBE
WC
SCE
AW
HA
SA
PWE
SD
HD
LZWE
HZWE
BW
Notes
10. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V.
6. t
7. t
8. At any given temperature and voltage condition, t
9. This parameter is guaranteed by design and is not tested.
[9]
[9]
and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that
terminates the Write.
POWER
HZOE
[6]
Parameter
, t
HZBE
gives the minimum amount of time that the power supply should be at typical V
[10]
, t
HZCE
, and t
HZWE
V
Read cycle time
Address to data valid
Data hold from address change
CE LOW to data valid
OE LOW to data valid
OE LOW to low-Z
OE HIGH to high-Z
CE LOW to low-Z
CE HIGH to high-Z
CE LOW to power-up
CE HIGH to power-down
Byte Enable to data valid
Byte Enable to low-Z
Byte Disable to high-Z
Write cycle time
CE LOW to write end
Address set-up to write end
Address hold from write end
Address set-up to write start
WE pulse width
Data set-up to write end
Data hold from write end
WE HIGH to low-Z
WE LOW to high-Z
Byte enable to end of write
CC
are specified with a load capacitance of 5 pF as in (c) of AC Test Loads. Transition is measured when the outputs enter a high impedance state.
(typical) to the first access
Over the Operating Range
[8]
[8]
HZCE
[8]
[7, 8]
[7, 8]
[7, 8]
Description
is less than t
LZCE
, t
HZOE
[5]
is less than t
CC
LZOE
values until the first memory access can be performed.
, and t
HZWE
is less than t
Min.
100
10
10
-10 (Ind’l/Auto-A)
3
0
3
0
0
8
8
0
0
7
5
0
3
7
LZWE
for any given device.
Max.
10
10
10
CY7C1021DV33
5
5
5
5
6
5
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Unit
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns