IS61C5128AS-25QLI ISSI, Integrated Silicon Solution Inc, IS61C5128AS-25QLI Datasheet - Page 11

• Manufacturer Part Number: IS61C5128AS-25QLI
• Description: IC SRAM 4MBIT 25NS 32SOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS61C5128AS-25QLI

• Format - Memory: RAM
• Memory Type: SRAM - Asynchronous
• Memory Size: 4M (512K x 8)
• Speed: 25ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-SOP
• Density: 4Mb
• Access Time (max): 25ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 19b
• Package Type: SOP
• Operating Temp Range: -40C to 85C
• Number Of Ports: 1
• Supply Current: 15mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Word Size: 8b
• Number Of Words: 512K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 706-1060-5

IS61C5128AL/AS
WRITE CYCLE NO. 2
WRITE CYCLE NO. 3
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
2. I/O will assume the High-Z state if OE
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
03/04/2008
ADDRESS
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
ADDRESS
D
D
OUT
WE
D
OE
CE
OUT
WE
D
OE
CE
IN
IN
LOW
LOW
LOW
t
SA
t
DATA UNDEFINED
SA
DATA UNDEFINED
(OE is HIGH During Write Cycle)
(OE is LOW During Write Cycle)
IS64C5128AL/AS
≥
V
IH
.
VALID ADDRESS
t
t
t
t
AW
HZWE
AW
HZWE
VALID ADDRESS
t
t
PWE1
WC
t
t
(1)
PWE2
(1,2)
WC
HIGH-Z
HIGH-Z
t
t
SD
SD
DATA
DATA
IN
IN
VALID
VALID
t
t
HD
HD
t
t
LZWE
LZWE
t
t
HA
HA
CE_WR2.eps
CE_WR3.eps
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