DS1200S+ Maxim Integrated, DS1200S+ Datasheet - Page 2

• Manufacturer Part Number: DS1200S+
• Description: SRAM
• Manufacturer: Maxim Integrated
• Series: DS1200r

Specifications of DS1200S+

• Rohs: yes
• Part # Aliases: 90-1200S+000

Figure 1. ELECTRONIC TAG BLOCK DIAGRAM
Figure 2. ADDRESS/COMMAND
OPERATION
The block diagram (Figure 1) illustrates the main elements of the device: shift register, control logic,
NV RAM, and power switch. To initiate a memory cycle, RST is taken high and 24 bits are loaded into
the shift register, providing both address and command information. Each bit is input serially on the
rising edge of the CLK input. Seven address bits specify one of the 128 RAM locations. The remaining
command bits specify read/write and byte/burst mode. After the first 24 clocks, which load the shift
register, additional clocks will output data for a read or input data for a write. The number of clock pulses
equal 24 plus 8 for byte mode or 24 plus 1024 for burst mode.
For hardwired applications, active power is supplied by the V
applications, power can be supplied by the RST pin.
B-BURST
R-READ
W-WRITE
7
B
6
0
5
0
BYTE 3
4
0
3
0
2
0
1
0
0
0
7
0
A6 A5 A4 A3 A2 A1 A0
6
5
4
BYTE 2
3
2
1
0
R
7
W
R
6
W
2 of 7
R
5
W
R
4
W
BYTE 1
R
3
W
R
2
W
R
1
W
R
CC
0
W
pin. Alternatively, for user-insertable