IS62WV5128BLL-55H-TR ISSI, IS62WV5128BLL-55H-TR Datasheet - Page 9

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IS62WV5128BLL-55H-TR

Manufacturer Part Number
IS62WV5128BLL-55H-TR
Description
SRAM 4Mb 512Kx8 55ns 2.5v-3.6v
Manufacturer
ISSI
Type
Asynchronousr
Datasheet

Specifications of IS62WV5128BLL-55H-TR

Product Category
SRAM
Memory Size
4 Mbit
Organization
512 K x 8
Access Time
55 ns
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.5 V
Maximum Operating Current
15 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Package / Case
TSOP-32
Interface
TTL
Factory Pack Quantity
2000
IS62WV5128ALL,
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
01/29/08
WRITE CYCLE SWITCHING CHARACTERISTICS
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4V to
2. The internal write time is defined by the overlap of CS1 LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CS1 Controlled, OE = HIGH or LOW)
Symbol
t
t
t
t
t
t
t
t
t
t
V
terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
WC
SCS1
AW
HA
SA
PWE
SD
HD
HZWE
LZWE
DD
ADDRESS
-0.2V/V
(3)
(3)
DOUT
CS1
DIN
DD
WE
-0.3V and output loading specified in Figure 1.
Parameter
Write Cycle Time
CS1 to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
IS62WV5128BLL
t
DATA UNDEFINED
SA
t
AW
t
HZWE
t
SCS1
t
WC
t
PWE
(1,2)
HIGH-Z
(Over Operating Range)
t
SD
DATA-IN VALID
Min.
45
45
40
25
55
0
0
5
0
55 ns
Max.
t
20
HA
t
t
LZWE
HD
Min.
70
60
60
30
50
0
0
0
5
70 ns
Max.
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9

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