IS61NLP51236-200TQLI ISSI, Integrated Silicon Solution Inc, IS61NLP51236-200TQLI Datasheet - Page 5

IC SRAM 18MBIT 200MHZ 100TQFP

IS61NLP51236-200TQLI

Manufacturer Part Number
IS61NLP51236-200TQLI
Description
IC SRAM 18MBIT 200MHZ 100TQFP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
Synchronousr
Datasheet

Specifications of IS61NLP51236-200TQLI

Memory Size
18M (512K x 36)
Package / Case
100-TQFP, 100-VQFP
Interface
Parallel
Format - Memory
RAM
Memory Type
SRAM - Synchronous
Speed
200MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Access Time
3.1 ns
Maximum Clock Frequency
200 MHz
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Maximum Operating Current
475 mA
Organization
512 K x 36
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Ports
4
Operating Supply Voltage
2.5 V to 3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
706-1103
IS61NLP51236-200TQLI

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IS61NLP51236-200TQLI
Manufacturer:
ISSI
Quantity:
135
Part Number:
IS61NLP51236-200TQLI
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
Part Number:
IS61NLP51236-200TQLI
Manufacturer:
ISSI
Quantity:
20 000
Part Number:
IS61NLP51236-200TQLI-TR
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
IS61NLP25672/IS61NVP25672 
IS61NLP51236/IS61NVP51236
IS61NLP102418/IS61NVP102418   
PIN CONFIgURATION   —  512K 
PIN DESCRIPTIONS
Integrated Silicon Solution, Inc. — www.issi.com
Rev.  M
01/06/2011
Note:
Symbol
A
A0, A1
ADV
WE
CLK
CKE
CE, CE2, CE2 Synchronous Chip Enable
BWx (x=a-d)
OE
ZZ
G
M
A
B
C
D
E
F
H
K
N
P
R
J
L
A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
MODE
DQPd
DQPc
DQc
DQc
DQc
DQc
DQd
DQd
DQd
DQd
NC
NC
NC
NC
1
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address Advance/
Load
Synchronous Read/Write Control
Input
Synchronous Clock
Clock Enable
Synchronous Byte Write Inputs
Output Enable
Power Sleep Mode
VDD
DQc
DQc
DQc
DQc
DQd
DQd
DQd
DQd
NC
NC
NC
NC
2
A
A
V
V
V
V
V
V
V
V
V
V
CE2
CE
NC
ddq
ddq
ddq
ddq
ddq
ddq
ddq
ddq
ddq
ddq
A
A
3
x
BWc
BWd
V
V
V
V
V
V
V
V
V
V
V
 36, 165-Ball PBgA (TOP VIEW) 
A
A
4
SS
SS
dd
dd
dd
dd
dd
dd
dd
dd
dd
BWb
BWa
TMS
V
V
V
V
V
V
V
V
V
V
TdI
NC
5
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
CE2
CLK
V
V
V
V
V
V
V
V
V
V
A1*
A0*
NC
6
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
MODE
TCK, TDI
TDO, TMS
V
NC
DQx
DQPx
V
V
DD
DDQ
SS
CKE
TDO
TCK
WE
V
V
V
V
V
V
V
V
V
V
NC
7
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
ADV
V
V
V
V
V
V
V
V
V
V
V
OE
Burst Sequence Selection
JTAG Pins
3.3V/2.5V Power Supply
No Connect
Data Inputs/Outputs
Parity Data I/O
Isolated output Power Supply
3.3V/2.5V
Ground
8
A
A
SS
dd
dd
dd
dd
dd
dd
dd
dd
dd
SS
V
V
V
V
V
V
V
V
V
V
NC
ddq
ddq
ddq
ddq
ddq
ddq
ddq
ddq
ddq
ddq
9
A
A
A
A
DQb
DQb
DQb
DQb
DQa
DQa
DQa
DQa
NC
NC
NC
10
A
A
A
A
DQPb
DQPa
DQb
DQb
DQb
DQb
DQa
DQa
DQa
DQa
NC
NC
NC
11
ZZ
A
5

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