MAX6708YKA+T Maxim Integrated, MAX6708YKA+T Datasheet - Page 17

• Manufacturer Part Number: MAX6708YKA+T
• Description: Supervisory Circuits uP Supervisor
• Manufacturer: Maxim Integrated
• Series: MAX6701, MAX6701A, MAX6702, MAX6702A, MAX6703, MAX6703A, MAX6704, MAX6705, MAX6705A, MAX6706, MAX6706A, MAX6707, MAX6707A, MAX6708r

Specifications of MAX6708YKA+T

• Rohs: yes
• Number Of Voltages Monitored: 1
• Monitored Voltage: 2.5 V, 3 V, 3.3 V, 5 V
• Undervoltage Threshold: 2.12 V
• Overvoltage Threshold: 2.25 V
• Output Type: Active High, Active Low, Push-Pull
• Manual Reset: Resettable
• Watchdog: No Watchdog
• Battery Backup Switching: No Backup
• Power-up Reset Delay (typ): 300 ms
• Supply Voltage - Max: 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-23
• Chip Enable Signals: No
• Maximum Power Dissipation: 714 mW
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: Yes
• Supply Current (typ): 6 uA
• Supply Voltage - Min: 1.2 V

Figure 12b. Timing Diagram Power-Down Modes, Internal Clock
The SHDN pin places the converter into the full
power-down mode. Unlike with the software shut-down
modes, conversion is not completed. It stops coinci-
dentally with SHDN being brought low. There is no
power-up delay if an external reference is used and is
not shut down. The SHDN pin also selects internal or
external reference compensation (see Table 7).
The MAX186/MAX188 auto power-down modes can
save considerable power when operating at less than
maximum sample rates. The following discussion illus-
trates the various power-down sequences.
Figure 13. MAX186 FULLPD/FASTPD Power-Up Sequence
CLOCK
SSTRB
MODE
MODE
DOUT
DIN
REFADJ
VREF
DIN
1
FULLPD
S X X X X X 1 0
2.5V
0V
4V
0V
0 0
______________________________________________________________________________________
Power-Down Sequencing
CONVERSION
SETS INTERNAL
CLOCK MODE
Hardware Power-Down
(ZEROS)
POWERED UP
COMPLETE CONVERSION SEQUENCE
DATA VALID
1
= RC = 20k x C
FASTPD
INTERNAL CLOCK MODE
2ms WAIT
0 1
REFADJ
S
X
The following examples illustrate two different power-down
sequences. Other combinations of clock rates, compen-
sation modes, and power-down modes may give lowest
power consumption in other applications.
Figure 14a depicts the MAX186 power consumption for
one or eight channel conversions utilizing full
power-down mode and internal reference compensation.
A 0.01µF bypass capacitor at REFADJ forms an RC filter
with the internal 20kΩ reference resistor with a 0.2ms
time constant. To achieve full 12-bit accuracy, 10 time
constants or 2ms are required after power-up. Waiting
2ms in FASTPD mode instead of full power-up will reduce
the power consumption by a factor of 10 or more. This is
achieved by using the sequence shown in Figure 13.
X
Low-Power, 8-Channel,
X
t
BUFFEN
X
1
X
0 0
NOPD
CH1
15µs
SETS FULL
POWER-DOWN
CONVERSION
Serial 12-Bit ADCs
1
1
1
FULLPD
CH7
Conversions/Channel/Second
DATA VALID
0 0
POWER-DOWN
Lowest Power at up to 500
FULL
(ZEROS)
1
FASTPD
S
POWERED
0 1
UP
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