M24C32-RMB6TG STMicroelectronics, M24C32-RMB6TG Datasheet - Page 6
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M24C32-RMB6TG
Manufacturer Part Number
M24C32-RMB6TG
Description
IC EEPROM 32KBIT 400KHZ 8UFDFPN
Manufacturer
STMicroelectronics
Specifications of M24C32-RMB6TG
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
32K (4K x 8)
Speed
400kHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-MLP, 8-UFDFPN
Organization
4 K x 8
Interface Type
I2C
Maximum Clock Frequency
0.4 MHz
Access Time
900 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.8 V
Maximum Operating Current
0.8 mA
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
2.5 V, 3.3 V, 5 V
Memory Configuration
4096 X 8
Clock Frequency
400kHz
Supply Voltage Range
1.8V To 5.5V
Memory Case Style
DFN
No. Of Pins
8
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-8705-2
M24C32-RMB6TG
M24C32-RMB6TG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M24C32-RMB6TG
Manufacturer:
ST
Quantity:
7 489
Description
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Description
The M24C32-W, M24C32-R and M24C32-F devices are I
erasable programmable memories (EEPROM). They are organized as 4096 × 8 bits.
Figure 1.
I
devices carry a built-in 4-bit device type identifier code (1010) in accordance with the I
bus definition.
The device behaves as a slave in the I
by the serial clock. Read and Write operations are initiated by a Start condition, generated
by the bus master. The Start condition is followed by a device select code and Read/Write
bit (RW) (as described in
When writing data to the memory, the device inserts an acknowledge bit during the 9
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the
bus master acknowledges the receipt of the data byte in the same way. Data transfers are
terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
2
C uses a two-wire serial interface, comprising a bidirectional data line and a clock line. The
Logic diagram
Table
Doc ID 4578 Rev 17
2), terminated by an acknowledge bit.
2
C protocol, with all memory operations synchronized
M24C32-W M24C32-R M24C32-F
2
C-compatible electrically
th
2
bit
C