MAX6830VIUT-T Maxim Integrated, MAX6830VIUT-T Datasheet - Page 8

• Manufacturer Part Number: MAX6830VIUT-T
• Description: Supervisory Circuits
• Manufacturer: Maxim Integrated
• Series: MAX6826, MAX6827, MAX6828, MAX6829, MAX6830, MAX6831r

Specifications of MAX6830VIUT-T

• Number Of Voltages Monitored: 2
• Monitored Voltage: 0.9 V to 2.5 V, 1.8 V to 5 V
• Undervoltage Threshold: 1.521 V, 1.343 V
• Overvoltage Threshold: 1.629 V, 1.433 V
• Output Type: Active High, Push-Pull
• Manual Reset: Resettable
• Watchdog: Watchdog
• Battery Backup Switching: No Backup
• Power-up Reset Delay (typ): 320 ms
• Supply Voltage - Max: 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-23
• Chip Enable Signals: No
• Maximum Power Dissipation: 696 mW
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: No
• Supply Current (typ): 10 uA
• Supply Voltage - Min: 1.2 V

Dual Ultra-Low-Voltage SOT23 µP Supervisors
with Manual Reset and Watchdog Timer
A microprocessor’s (µP’s) reset input starts the µP in a
known state. The MAX6826–MAX6831 µP supervisory
circuits assert a reset to prevent code-execution errors
during power-up, power-down, and brownout condi-
tions. Whenever a monitored voltage falls below the
reset threshold, the reset output asserts low for RESET
and high for RESET. Once all monitored voltages
exceed their reset thresholds, an internal timer keeps
the reset output asserted for the specified reset timeout
period (t
original state (Figure 3).
Many µP-based products require manual-reset capabil-
ity, allowing the operator, a test technician, or external
logic circuitry to initiate a reset. A logic low on MR
Figure 2. Functional Diagram of V
8
_______________________________________________________________________________________
RP
); after this interval, reset output returns to its
V
WDI
V
MR
CC2
CC
Detailed Description
RESET /RESET Output
CC2
Manual Reset Input
0.63V
WATCHDOG
TRANSITION
DETECTOR
1.26V
V
CC
asserts a reset. Reset remains asserted while MR is
low, and for the timeout period (140ms min) after it
returns high. MR has an internal 50kΩ pullup resistor,
so it can be left open if not used. This input can be dri-
ven with CMOS logic levels or with open-drain/collector
Figure 3. Reset Timing Diagram
DELAY GENERATOR
RESET TIMEOUT
WATCHDOG
MAX6829/MAX6830/MAX6831
TIMER
GND
RESET
RESET
V
1V
CC
V
TH
t
t
RP
RP
RESET
OR
RESET
V
TH
1V
t
t
RD
RD