M24256-BWMN6TP STMicroelectronics, M24256-BWMN6TP Datasheet - Page 29

• Manufacturer Part Number: M24256-BWMN6TP
• Description: IC EEPROM 256KBIT 400KHZ 8SOIC
• Manufacturer: STMicroelectronics

Specifications of M24256-BWMN6TP

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 256K (32K x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Density: 256Kb
• Interface Type: Serial (I2C)
• Organization: 32Kx8
• Access Time (max): 900ns
• Frequency (max): 400KHz
• Write Protection: Yes
• Data Retention: 40Year
• Operating Supply Voltage (typ): 3.3/5V
• Package Type: SOIC
• Operating Temp Range: -40C to 85C
• Supply Current: 5mA
• Operating Supply Voltage (min): 2.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Maximum Clock Frequency: 0.4 MHz
• Access Time: 900 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 5 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8623-2; M24256-BWMN6TP

M24256-BF, M24256-BR, M24256-BW, M24256-DR
Table 17.
1. Only new M24256-BR and M24256-DR devices identified by the process letter K are qualified at 1 MHz.
2. All values are referred to V
3. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
4. Characterized only, not tested in production.
5. With C
6. The new M24xxx devices (identified by the process letter K) offer t
7. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
8. t
9. The new M24xxx devices (identified with the process letter K) offer t
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
C
CHCL
CLCH
XH1XH2
XL1XL2
QL1QL2
DXCX
CLDX
CLQX
CLQV
CHDL
DLCL
CHDH
DHDL
W
NS
Symbol
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
f
(min) which is an improved value compared to the t
current M24xxx devices (identified with the Process letter A)
rising edge of SDA.
0.7V
value compared to the current M24xxx devices (identified by the process letter A).
(4)
C
CLQV
< 400 kHz, or less than 120 ns when f
(7)(8)
CC
(4)
is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3V
L
, assuming that the R
= 10 pF.
1 MHz AC characteristics
f
t
t
t
t
t
t
t
t
t
t
t
t
SCL
HIGH
LOW
R
F
F
SU:DAT
SU:STA
HD:STA
SU:STO
BUF
WR
HD:DAT
Alt.
t
t
DH
AA
Clock frequency
Clock pulse width high
Clock pulse width low
Input signal rise time
Input signal fall time
SDA (out) fall time
Data in setup time
Data in hold time
Data out hold time
Clock low to next data valid (access time)
Start condition setup time
Start condition hold time
Stop condition setup time
Time between Stop condition and next
Start condition
Write time
Pulse width ignored (input filter on SCL and
SDA)
Test conditions specified in
IL
(max) and V
bus
× C
Doc ID 6757 Rev 21
bus
time constant is within the values specified in
C
IH
Parameter
(min).
< 1 MHz.
(1)
CLQX
=50 ns (min) and t
Table 9
CLQX
and
NS
= 80 ns (min) which is an improved
=100 ns (min) and t
Table 11
CLQV
0
300
400
(3)
(3)
20
80
0
50
50
250
250
250
500
-
-
Min.
(5)
(6)
(6)
=50 ns (min) offered by the
DC and AC parameters
(2)
Figure
1
-
-
(3)
(3)
120
-
-
-
500
-
-
-
-
5
50
Max.
(9)
CLQV
6.
(2)
=100 ns
CC
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
or
Unit
29/42