M24256-BRDW6TP STMicroelectronics, M24256-BRDW6TP Datasheet
M24256-BRDW6TP
Specifications of M24256-BRDW6TP
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M24256-BRDW6TP Summary of contents
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... More than 40-year data retention ■ Packages ® – ECOPACK (RoHS compliant) March 2010 M24256-BF M24256-BR M24256-BW M24256-DR 256 Kbit serial I²C bus EEPROM with three Chip Enable lines 2 C 208 mils width 150 mils width TSSOP8 (DW) UFDFPN8 (MB) 2 × (MLP) ...
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... Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.7 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.8 Page Write (memory array 3.9 Identification Page Write (M24256-DR only 3.10 Lock Identification Page (M24256-DR only 3.11 ECC (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . . . 17 3.12 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 19 3.13 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.14 Random Address Read (in memory array ...
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... M24256-BF, M24256-BR, M24256-BW, M24256-DR 3.18 Read Identification Page status (locked/unlocked 3.19 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Doc ID 6757 Rev 21 Contents 3/42 ...
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... List of tables List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Device select code (for memory array Table 3. Device select code to access the Identification page (M24256-DR only Table 4. Most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 5. Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 6. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 8 ...
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... M24256-BF, M24256-BR, M24256-BW, M24256-DR List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. WLCSP connections (top view, marking side, with balls on the underside Figure 4. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Figure Fast mode (f C bus parasitic capacitance (C 2 Figure Fast mode Plus (f bus parasitic capacitance (C 2 Figure 7 ...
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... Description The M24256-Bx devices are I (EEPROM). They are organized × 8 bits. The M24256-Bx and M24256-DR can decode the type identifier code (1010) in accordance 2 with the I C bus definition. The M24256-DR also decodes the type identifier code (1011) when accessing the identification page. ...
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... M24256-BF, M24256-BR, M24256-BW, M24256-DR Figure 2. Package connections 1. See Package mechanical data Figure 3. WLCSP connections (top view, marking side, with balls on the underside SCL SDA section for package dimensions, and how to identify pin- SDA V SCL SS Doc ID 6757 Rev 21 Description AI04035e ai14712 7/42 ...
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... Control (WC) is driven High. When unconnected, the signal is internally read as V Write operations are allowed. When Write Control (WC) is driven High, device select and address bytes are acknowledged, Data bytes are not acknowledged. 8/42 M24256-BF, M24256-BR, M24256-BW, M24256-DR indicates how the value of the pull-up resistor can be calculated M24xxx ...
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... M24256-BF, M24256-BR, M24256-BW, M24256-DR 2.5 V ground the reference for the V SS 2.6 Supply voltage (V 2.6.1 Operating supply voltage V Prior to selecting the memory and issuing instructions to it, a valid and stable V within the specified [V Table 10). In order to secure a stable DC supply voltage recommended to decouple the ...
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... Figure Fast mode Plus (f bus parasitic capacitance (C 100 Bus line capacitor (pF) 10/42 M24256-BF, M24256-BR, M24256-BW, M24256-DR = 400 kHz): maximum bus When time constant must be below the 400 ns time constant line represented on the left 100 1000 Bus line capacitor (pF) ...
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... The most significant bit, b7, is sent first. 2. E0, E1 and E2 are compared against the respective external pins on the memory device. Table 3. Device select code to access the Identification page (M24256-DR only) Device select code 1. The most significant bit, b7, is sent first. 2. E0, E1 and E2 are compared against the respective external pins on the memory device. ...
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... Signal description Table 4. Most significant address byte b15 b14 Table 5. Least significant address byte b7 b6 12/42 M24256-BF, M24256-BR, M24256-BW, M24256-DR b13 b12 b11 Doc ID 6757 Rev 21 b10 ...
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... M24256-BF, M24256-BR, M24256-BW, M24256-DR 3 Device operation The device supports the I data on to the bus is defined transmitter, and any device that reads the data receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization ...
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... Serial Data (SDA) during the 9 the device select code, it deselects itself from the bus, and goes into Standby mode. Table 6. Operating modes Mode Current Address Read Random Address Read Sequential Read Byte Write Page Write 14/42 M24256-BF, M24256-BR, M24256-BW, M24256-DR (1) RW bit WC Bytes ...
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... M24256-BF, M24256-BR, M24256-BW, M24256-DR Figure 8. Write mode sequences with (data write inhibited) WC Byte Write WC Page Write WC (cont'd) Page Write (cont'd) ACK ACK Dev sel Byte addr Byte addr R/W ACK ACK Dev sel Byte addr Byte addr R/W NO ACK NO ACK Data in N ...
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... NoAck. After each byte is transferred, the internal byte address counter (the 7 least significant address bits only) is incremented. The transfer is terminated by the bus master generating a Stop condition. 16/42 M24256-BF, M24256-BR, M24256-BW, M24256-DR , and the successful completion of a Write operation, W Figure 9. ...
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... It is therefore recommended to write by word (4 bytes) in order to benefit from the larger amount of Write cycles. The M24256-Bx and M24256-DR devices are qualified at 1 million (1 000 000) Write cycles, using a cycling routine that writes to the device by multiples of 4-bytes. Doc ID 6757 Rev 21 ...
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... Device operation Figure 9. Write mode sequences with (data write enabled) WC Byte Write WC Page Write WC (cont'd) Page Write (cont'd) 18/42 M24256-BF, M24256-BR, M24256-BW, M24256-DR ACK ACK Dev sel Byte addr Byte addr R/W ACK ACK Dev sel Byte addr Byte addr R/W ...
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... M24256-BF, M24256-BR, M24256-BW, M24256-DR Figure 10. Write cycle polling flowchart using ACK First byte of instruction with already decoded by the device 3.12 Minimizing system delays by polling on ACK During the internal Write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum Write time (t ...
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... Read/Write bit (RW) set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition. 20/42 M24256-BF, M24256-BR, M24256-BW, M24256-DR ACK NO ACK Dev sel ...
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... M24256-BF, M24256-BR, M24256-BW, M24256-DR 3.15 Current Address Read (in memory array) For the Current Address Read operation, following a Start condition, the bus master only sends a device select code with the Read/Write bit (RW) set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented ...
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... For all Read instructions, the device waits, after each byte read, for an acknowledgment th during the 9 bit time. If the bus master does not drive Serial Data (SDA) Low during this time, the device terminates the data transfer and switches to its Standby mode. 22/42 M24256-BF, M24256-BR, M24256-BW, M24256-DR Doc ID 6757 Rev 21 ...
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... M24256-BF, M24256-BR, M24256-BW, M24256-DR 4 Initial delivery state The device is delivered with all bits in the memory array set to 1 (each byte contains FFh). 5 Maximum rating Stressing the device outside the ratings listed in the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied ...
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... Symbol C Load capacitance L Input rise and fall times Input levels Input and output timing reference levels Figure 12. AC test measurement I/O waveform 24/42 M24256-BF, M24256-BR, M24256-BW, M24256-DR Parameter Parameter Parameter Parameter Input Levels Timing Reference Levels 0.8V CC 0.2V CC Doc ID 6757 Rev 21 Min ...
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... M24256-BF, M24256-BR, M24256-BW, M24256-DR Table 12. Input parameters Symbol C Input capacitance (SDA Input capacitance (other pins) IN Input impedance ( (E2, E1, E0, WC) Input impedance ( (E2, E1, E0, WC) 1. Sampled only, not 100% tested. 2. E2,E1,E0: Input impedance when the memory is selected (after a Start condition). Table 13. DC characteristics (voltage range W) ...
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... Output low voltage OL 1. Only for devices operating Characterized value, not tested in production. 3. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the completion of the internal write cycle t 26/42 M24256-BF, M24256-BR, M24256-BW, M24256-DR Test conditions (in addition to those in Table ...
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... M24256-BF, M24256-BR, M24256-BW, M24256-DR Table 15. DC characteristics (voltage range F) Symbol Parameter Input leakage current I LI (E1, E2, SCL, SDA) I Output leakage current LO I Supply current (Read Supply current (Write) CC0 I Standby supply current CC1 Input low voltage V IL (SCL, SDA, WC) Input high voltage ...
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... SCL) required by the SDA bus line to reach either 0.3V CLQV 0.7V , assuming that The current M24xxx devices (identified by the Process letter A) offer t BR and M24256-DR device (identified by the process letter K) offer t safe margin compared to the 50 ns minimum value recommended by the I 28/42 M24256-BF, M24256-BR, M24256-BW, M24256-DR Table 8, ...
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... NS 1. Only new M24256-BR and M24256-DR devices identified by the process letter K are qualified at 1 MHz. 2. All values are referred There is no min. or max. values for the input signal rise and fall times however recommended by the I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when f < ...
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... SCL tDLCL SDA In tCHDL tXH1XH2 Start condition SCL SDA In tCHDH Stop condition SCL tCLQV SDA Out 30/42 M24256-BF, M24256-BR, M24256-BW, M24256-DR tCHCL tCLCH tCLDX tDXCH SDA Change SDA Input tW Write cycle tCHCL tCLQX Data valid Data valid Doc ID 6757 Rev 21 tXL1XL2 ...
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... M24256-BF, M24256-BR, M24256-BW, M24256-DR 7 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK trademark. Figure 14. SO8W – 8-lead plastic small outline, 208 mils body width, package outline 1 ...
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... SO8N – 8-lead plastic small outline, 150 mils body width, package mechanical data Symbol ccc Values in inches are converted from mm and rounded to 4 decimal digits. 32/42 M24256-BF, M24256-BR, M24256-BW, M24256-DR A ccc millimeters Typ Min Max 1.75 0.1 0.25 1.25 0.28 0.48 ...
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... M24256-BF, M24256-BR, M24256-BW, M24256-DR Figure 16. TSSOP8 – 8-lead thin shrink small outline, package outline Drawing is not to scale. Table 20. TSSOP8 – 8-lead thin shrink small outline, package mechanical data Symbol Values in inches are converted from mm and rounded to 4 decimal digits millimeters ...
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... (2) ddd 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from measuring. 34/42 M24256-BF, M24256-BR, M24256-BW, M24256- ddd A1 millimeters Typ Min Max 0.55 0.45 0.6 0.02 0 0.05 ...
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... M24256-BF, M24256-BR, M24256-BW, M24256-DR Figure 18. WLCSP, 0.5 mm pitch, package outline Drawing is not to scale. Table 22. WLCSP 0.5 mm pitch, package mechanical data Symbol A 0.60 A1 0.245 A2 0.355 B D 1.97 E 1.785 e 0.5 e1 0.866 e2 0.25 e3 0.433 F 0.552 G 0.392 ( Preliminary data. 2. Values in inches are converted from mm and rounded to 4 decimal digits. ...
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... Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. 36/42 M24256-BF, M24256-BR, M24256-BW, M24256-DR M24256–B W (1) Doc ID 6757 Rev 21 ...
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... M24256-BF, M24256-BR, M24256-BW, M24256-DR Table 24. Available M24256-BR, M24256-BW, M24256-BF products (package, voltage range, temperature grade) Package SO8N (MN) SO8W (MW) TSSOP (DW) WLCSP (CS) UFDFPN8 (MB) Table 25. Available M24256-DR products (package, voltage range, temperature grade) SO8N (MN) TSSOP (DW) M24256-BW 2 5.5 V Range 6, Range 3 Range 6 Range Package Doc ID 6757 Rev 21 ...
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... M24256-BF, M24256-BR, M24256-BW, M24256-DR Lead Soldering Temperature in the Absolute Maximum Ratings table amended Write Cycle Polling Flow Chart using ACK illustration updated 1.1 LGA8 and SO8(wide) packages added References to PSDIP8 changed to PDIP8, and Package Mechanical data ...
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... R) Note 1 removed from Table 13: DC characteristics (voltage range SO8W package specifications modified in data. Table 24: Available M24256-BR, M24256-BW, M24256-BF products (package, voltage range, temperature grade) M24512-x products (package, voltage range, temperature grade) Section 2.5: VSS ground added. Small text changes. ...
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... Figure 6: I2C Fast mode Plus ( MHz): maximum Rbus value versus 10 bus parasitic capacitance (Cbus) on page 10 Caution removed in Section 3.11: ECC (error correction code) and write cycling. M24512-W and M24256-BW offered in the device grade 3 option (automotive temperature range): – Table 8: Operating conditions (voltage range – Table 13: DC characteristics (voltage range – ...
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... CHDL – t and t values removed XH1XH2 XL1XL2 – Notes modified Figure 13: AC waveforms Section 3.9: Identification Page Write (M24256-DR only) 18 corrected.Section 3.17: Read Identification Page UFDFPN8 package is now offered (see data, Table 23: Ordering information scheme 19 M24256-BR, M24256-BW, M24256-BF products (package, voltage range, temperature grade) ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 42/42 M24256-BF, M24256-BR, M24256-BW, M24256-DR Please Read Carefully: © 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies www ...