M95256-WMN6P STMicroelectronics, M95256-WMN6P Datasheet - Page 19

• Manufacturer Part Number: M95256-WMN6P
• Description: IC EEPROM 256KBIT 5MHZ 8SOIC
• Manufacturer: STMicroelectronics

Specifications of M95256-WMN6P

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 256K (32K x 8)
• Speed: 5MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Organization: 32 K x 8
• Interface Type: SPI
• Maximum Clock Frequency: 5 MHz
• Access Time: 60 ns
• Supply Voltage (max): 6.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 5 mA
• Maximum Operating Temperature: + 130 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 5.5 V
• Memory Configuration: 32K X 8
• Ic Interface Type: Serial, SPI
• Clock Frequency: 20MHz
• Supply Voltage Range: 2.5V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-6357-5; M95256-WMN6P

M95256-DR, M95256, M95256-W, M95256-R
The protection features of the device are summarized in
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register (provided that the WEL bit has
previously been set by a WREN instruction), regardless of the logic level applied on the
Write Protect (W) input pin.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two
cases need to be considered, depending on the state of Write Protect (W) input pin:
●
●
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be
entered:
●
●
Once entered in the Hardware Protected mode (HPM), the only way to exit the HPM mode is
to pull high the Write Protect (W) input pin.
If Write Protect (W) input pin is permanently tied high, the Hardware Protected mode (HPM)
can never be activated, and only the Software Protected mode (SPM), using the Block
Protect (BP1, BP0) bits of the Status Register, can be used.
Figure 9.
If Write Protect (W) input pin is driven high, it is possible to write to the Status Register
(provided that the WEL bit has previously been set by a WREN instruction.
If Write Protect (W) input pin is driven low, it is not possible to write to the Status
Register even if the WEL bit has previously been set by a WREN instruction. (Attempts
to write to the Status Register are rejected, and are not accepted for execution). As a
consequence, all the data bytes in the memory area that are software protected (SPM)
by the Block Protect (BP1, BP0) bits of the Status Register, are also hardware
protected against data modification.
either by setting the SRWD bit after driving Write Protect (W) input pin low,
or by driving Write Protect (W) input pin low after setting the SRWD bit.
S
C
D
Q
Write Status Register (WRSR) sequence
0
1
High Impedance
Doc ID 12276 Rev 11
2
Instruction
3
4
5
6
7
MSB
7
8
6
9 10 11 12 13 14 15
5
Register In
4
Status
Table
3
2
6.
1
0
AI02282D
Instructions
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