CY62256VNLL-70SNXI Cypress Semiconductor Corp, CY62256VNLL-70SNXI Datasheet - Page 7

• Manufacturer Part Number: CY62256VNLL-70SNXI
• Description: IC SRAM 256KBIT 70NS 28SOIC
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY62256VNLL-70SNXI

• Memory Size: 256K (32K x 8)
• Package / Case: 28-SOIC (7.5mm Width)
• Format - Memory: RAM
• Memory Type: SRAM
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 70 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 30 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 3 V
• Memory Configuration: 32K X 8
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: NSOIC
• No. Of Pins: 28
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2001-5

Switching Waveforms
Notes
Document Number: 001-06512 Rev. *D
14. Device is continuously selected. OE, CE = V
15. WE is HIGH for read cycle.
16. Address valid prior to or coincident with CE transition LOW.
17. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
18. Data I/O is high impedance if OE = V
19. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.
20. During this period, the I/Os are in output state and input signals should not be applied.
DATA OUT
ADDRESS
DATA OUT
CURRENT
ADDRESS
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
DATA I/O
SUPPLY
V
WE
OE
CE
OE
CE
CC
NOTE 20
PREVIOUS DATA VALID
HIGH IMPEDANCE
t
PU
t
IH
LZCE
t
SA
.
t
HZOE
Figure 5. Write Cycle No. 1 (WE Controlled)
t
t
ACE
LZOE
IL
.
t
OHA
50%
t
DOE
Figure 3. Read Cycle No. 1
Figure 4. Read Cycle No. 2
t
AA
t
AW
t
RC
t
WC
t
RC
DATA
t
t
PWE
SD
IN
[14, 15]
[15, 16]
VALID
DATA VALID
[17, 18, 19]
DATA VALID
t
HA
t
HD
t
t
HZOE
HZCE
t
PD
50%
CY62256VN
IMPEDANCE
HIGH
Page 7 of 14
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