MAX802LESA+T Maxim Integrated, MAX802LESA+T Datasheet - Page 6

• Manufacturer Part Number: MAX802LESA+T
• Description: Supervisory Circuits
• Manufacturer: Maxim Integrated
• Series: MAX690A, MAX692A, MAX802L, MAX802M, MAX805Lr

Specifications of MAX802LESA+T

• Number Of Voltages Monitored: 1
• Monitored Voltage: 4.65 V
• Undervoltage Threshold: 4.5 V
• Overvoltage Threshold: 4.75 V
• Output Type: Active Low, Push-Pull
• Manual Reset: Not Resettable
• Watchdog: Watchdog
• Battery Backup Switching: Backup
• Power-up Reset Delay (typ): 280 ms
• Supply Voltage - Max: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8 Narrow
• Chip Enable Signals: No
• Maximum Power Dissipation: 471 mW
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: Yes
• Supply Current (typ): 500 uA
• Supply Voltage - Min: 1.2 V

The MAX3691 features LVDS inputs and outputs for
interfacing with high-speed digital circuitry. The LVDS
standard is based on the IEEE 1596.3 LVDS specifi-
cation. This technology uses 250mV–400mV differen-
tial low-voltage swings to achieve fast transition
times, minimized power dissipation, and noise immu-
nity.
For proper operation, the parallel-clock LVDS outputs
(PCLKO+, PCLKO-) require 100Ω differential DC termi-
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
with Clock Synthesis and LVDS Inputs
Figure 2. Timing Diagram
6
_______________________________________________________________________________________
Low-Voltage Differential-Signal (LVDS)
PCLKO
PCLKI
PD_
SD
NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, PCLKO = (PCLKO+) - (PCLKO-).
*PD3 = D3; PD2 = D2; PD1 = D1; PD0 = D0.
VALID PARALLEL DATA*
Inputs and Outputs
t
SU
t
SKEW
t
H
nation between the inverting and noninverting outputs.
Do not terminate these outputs to ground.
The parallel data and parallel clock LVDS inputs (PD_+,
PD_-, PCLKI+, PCLKI-) are internally terminated with
100Ω differential input resistance, and therefore do not
require external termination.
The serial-data PECL outputs (SD+, SD-) require 50Ω
DC termination to (V
Output Termination section.
D3
D2
CC
D1
- 2V). See the Alternative PECL-
D0
PECL Outputs